amd6502
Senior member
- Apr 21, 2017
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I wanted him to answer the question as the claim was that the front end was not efficient because the SMT yield was greater.
statement I replied to:
"The SMT yield is higher, which means that the front end is still not efficiently feeding the execution units."
I don't see how that would work. The front end is probably pushed to its max during full load (both threads active). If the SMT yield is higher it kind of points to the front end doing its job. However, there isn't a way of knowning; perhaps if the the front end were improved, the SMT yield would rise even further. Basically, I don't think there's any info, and that statement doesn't make sense.
But it does seem plausible the 4-wide decoder could be holding back performance. (The likelyhood also increases if AMD goes beyond SMT2.)
It seems the improved SMT yield is probably mostly from the wider core (up to 3 loads per cycle now).
Now the big question is, where will they widen the core next (assuming it's widened in Zen3).
It could very well be that the width remains the same (4+3).
Would increasing the maximum writes/stores per cycle from 1 to 2 cause a lot of issues or complexity?
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