Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[StefanR5R]

AMD reportedly set to launch EPYC 4004 series for AM5 socket - VideoCardz.com

AMD preparing EPYC 4004 series Will use the AM5 package. Consumer Raphael chips will soon be available in a new variant. The data-center-oriented EPYC series is said to receive a new variant called 4004. The series will join an extended lineup of EPYC Zen4 CPUs, which now span across 5 segments...

videocardz.com

Ooh interesting. Epyc branded Raphael is coming on AM5. Maybe a 32 core Zen 4c?

From a few days ago:
For a brief period, seven models were posted on e-bay by seller pccompd, four EPYC 4##4P models and three EPYC 4##4PX models.
https://www.chiphell.com/thread-2601495-1-1.html

 

[StefanR5R]

On the question what might set EPYC 4004P apart from Ryzen and Ryzen Pro, besides the branding:

• The degree of commitment to ECC UDIMM qualification? It should, if it is called EPYC!

• As I commented earlier, I doubt that there will be new CCD configurations relative to Ryzen, such as dual V-cache.

• As yet unknown dormant I/O die features enabled? I doubt that too.
  Apropos, I believe I had read somewhere (can't remember where) that EPYC 9004's I/O die had a little dormant audio chip section, for use by Threadripper 7000. I might misremember or that claim may have been wrong though.

• Working "NUMA Nodes per Socket (NPS)" or "ACPI SRAT L3 Cache as NUMA Domain" option in the BIOS? Although this occurs to me as something which any BIOS maker could implement for any Ryzen already.
  (NPS was originally invented to reduce crosstalk within the big EPYC 7002 I/O die, which is made up of four quadrants with slightly added cost of traffic between GMIs in one quadrant and IMCs in another quadrant. That's still the case with EPYC 9004's I/O die, but naturally never was with Ryzen's little I/O die. But an NPS2 option for Ryzen would coerce NUMA-aware operating systems into a L3$-local scheduling policy. Though this purpose is actually what the mentioned ACPI BIOS option is for, specifically.)

 

[DrMrLordX]

EPYC 4004P

Does anyone else find it amusing that, after all these years, AMD finally has a 4004 CPU? They're only 53 years behind Intel!

 

[igor_kavinski]

Unfortunately that's just what the series will be called.

Some of the leaked model names:

• AMD Epyc 4244P
• AMD Epyc 4344P
• AMD Epyc 4364P
• AMD Epyc 4564P
• AMD Epyc 4384PX
• AMD Epyc 4484PX
• AMD Epyc 4584PX

2nd digit is the performance tier so higher number means better performance when core count is same.
Third digit is the core count so max 8 cores 16 threads.
4th digit is generation so all of these will be Genoa.
P means no dual socket support and X stands for V-cache.

Despite the low core count, I plan to get the last one if it's reasonably priced.

 

[gdansk]

Despite the low core count, I plan to get the last one if it's reasonably priced.

Why? It's just Raphael and it'll likely always be more expensive than consumer Raphael.
And the boards will be the same. Also never count out more cores due to a naming scheme: they can use hexadecimal for the model numbers if they add 12/16 cores later.

 

[igor_kavinski]

Why?

Because hopefully it will have 768MB or even 1.1GB of L3!

I bet there are Linux distros that could run RAM-less with that much cache.

Would be fun running tiny compiled C/C++ programs on such a distro and maybe even emulators. Purely for the novelty factor.

And benchmarking games with regular RAM and dGPU to see which one really, really flies with that much cache. That should be fun.

 

[StefanR5R]

2nd digit is the performance tier so higher number means better performance when core count is same.
Third digit is the core count

I don't think so.
Here is the Genoa series naming scheme for comparison:

Spoiler: It's product series | core count in the series | performance relative to core count | generation | feature modifier

(source)
Bergamo and Siena basically follow the same scheme.

On the question what might set EPYC 4004P apart from Ryzen and Ryzen Pro, besides the branding:

I forgot one item: Default TDP/PPT might differ from same core count Ryzen models. Or, I am in fact tempted to say, they really really should differ!

 

[igor_kavinski]

Spoiler: It's product series | core count in the series | performance relative to core count | generation | feature modifier

Thanks!

So core count will range from 24 to 64!!!

I don't think it's gonna be cheap then

 

[StefanR5R]

Nah, it's core-count-within-the-series, not just plain core-count.
That is, the core count symbols of the EPYC 4000 series won't be the same as in the EPYC 9000 series, nor as in the 8000 series.

My guess is that the three EPYC 4004PX models (if that leak had merit) are corresponding 1:1 with the three presently available Ryzen X3D models.¹
That is,

EPYC 4584PX <---> Ryzen 9 7950X3D (8c+8c, 1x V-cache)
EPYC 4484PX <---> Ryzen 9 7900X3D (6c+6c, 1x V-cache)
EPYC 4384PX <---> Ryzen 7 7800 X3D (8c w/ V-cache)​

and thus

EPYC 4564P <----> 8c+8c
EPYC 4364P <----> 8c
EPYC 4344P <----> 8c, lower PPT than EPYC 4364P
EPYC 4244P <----> 6c​

(Again, just a guess.)

________
¹) Edit: I meant to say Ryzen 7000X3D models, of course.

 

[igor_kavinski]

But massive L3 cache, right? RIGHT???

 

[Abwx]

But massive L3 cache, right? RIGHT??

With two CCDs this cant be more than 128MB, if this ever happen, and wich is far from being likely.

 

[maddie]

With two CCDs this cant be more than 128MB, if this ever happen, and wich is far from being likely.

Go with the flow.

It'll have quad layer 3D-Vcache. 512MB for the win.

 

[StefanR5R]

@igor_kavinski, on the one hand, _all_ currently available EPYCs and Xeons, including the Raptor Lake LGA1700 Xeon E-2400, contain only homogeneous cores. (All cores of a given CPU are of the same microarchitecture and have the same amounts of private and shared cache available to them.¹) If AMD were to make a 3D V-Cache™ equipped AM5 Zen4 EPYC with two CCDs in it, then both CCDs obviously would have to have their own V-cache if such a CPU was supposed to feature homogeneous performance across all cores too.

On the other hand, there is going to be a certain limit to the efforts which AMD would put into a new AM5 Zen4 EPYC series. We shall see where this limit is.

________
¹) Admittedly, there is sometimes a tiny asymmetry between cores by way of the various CPU-internal fabrics, notable the ring buses/ meshes/ … which connect cores with shared cache and memory controllers. A striking example of that was the Broadwell-EP MCC die. But the meshes in current Xeon SPs aren't entirely symmetric either, I presume. Little is known about the corresponding internal bus topology of AMD's CCDs and IODs.

 

[igor_kavinski]

On the other hand, there is going to be a certain limit to the efforts which AMD would put into a new AM5 Zen4 EPYC series. We shall see where this limit is.

AMD (or rather Lisa Su) values customer feedback more than Intel. They must've received quite a lot of requests from interested parties (private individuals, professionals and business entities) to make Epyc CPUs available on AM5. Not everyone wants to buy an expensive server mobo and a lot of them are really bland. Then there are people who value stability above everything else and want it at a cheaper price point than investing in a TR workstation or an Epyc server platform. I'm positive that AMD is responding to all of the aforementioned needs and possibly more use cases that I'm unaware of.

By the way, I plan to do gaming on my existing Epyc 7002 series CPU with 128 threads and it would be so funny to see which games crap out after seeing so many available cores/threads

 

[Markfw]

AMD (or rather Lisa Su) values customer feedback more than Intel. They must've received quite a lot of requests from interested parties (private individuals, professionals and business entities) to make Epyc CPUs available on AM5. Not everyone wants to buy an expensive server mobo and a lot of them are really bland. Then there are people who value stability above everything else and want it at a cheaper price point than investing in a TR workstation or an Epyc server platform. I'm positive that AMD is responding to all of the aforementioned needs and possibly more use cases that I'm unaware of.

By the way, I plan to do gaming on my existing Epyc 7002 series CPU with 128 threads and it would be so funny to see which games crap out after seeing so many available cores/threads

@StefanR5R , FYI, he has my old 7742 ES Rome CPU, in case it makes any difference to any of this.

 

[StefanR5R]

By the way, I plan to do gaming on my existing Epyc 7002 series CPU with 128 threads and it would be so funny to see which games crap out after seeing so many available cores/threads

The threads which the games are leaving idle can support TeAm AnandTech in the BOINC Pentathlon, starting tomorrow¹ May 4, 20:00 EDT/ 17:00 PDT. :-)
________
¹) or the day after tomorrow in time zones East of the prime meridian

 

[igor_kavinski]

The threads which the games are leaving idle can support TeAm AnandTech in the BOINC Pentathlon, starting tomorrow¹ May 4, 20:00 EDT/ 17:00 PDT. :-)
________
¹) or the day after tomorrow in time zones East of the prime meridian

The landlord pays the electricity bill. Don't want to burden him.

 

[StefanR5R]

True; neither the hardware nor the juice pumped through it should be borrowed from somebody who doesn't know it or doesn't want it, naturally.

 

[biostud]

Nah, it's core-count-within-the-series, not just plain core-count.
That is, the core count symbols of the EPYC 4000 series won't be the same as in the EPYC 9000 series, nor as in the 8000 series.

My guess is that the three EPYC 4004PX models (if that leak had merit) are corresponding 1:1 with the three presently available Ryzen X3D models.¹
That is,

EPYC 4584PX <---> Ryzen 9 7950X3D (8c+8c, 1x V-cache)​

EPYC 4484PX <---> Ryzen 9 7900X3D (6c+6c, 1x V-cache)​

EPYC 4384PX <---> Ryzen 7 7800 X3D (8c w/ V-cache)​

and thus

EPYC 4564P <----> 8c+8c​

EPYC 4364P <----> 8c​

EPYC 4344P <----> 8c, lower PPT than EPYC 4364P​

EPYC 4244P <----> 6c​

(Again, just a guess.)

________
¹) Edit: I meant to say Ryzen 7000X3D models, of course.

Is there any reason that AMD Epyc 4584PX and EPYC 4484PX couldn't be 2x V-cache?

Ryzen 9 7950X3D surfaces with 192MB L3 cache, 64MB more than retail CPU — may be an ES CPU or software detection error

An engineering sample that looks like a Windows bug, or vice versa?

www.tomshardware.com

 

[Abwx]

Is there any reason that AMD Epyc 4584PX and EPYC 4484PX couldn't be 2x V-cache?

Ryzen 9 7950X3D surfaces with 192MB L3 cache, 64MB more than retail CPU — may be an ES CPU or software detection error

An engineering sample that looks like a Windows bug, or vice versa?

www.tomshardware.com

There s none, if there s a substancial demand they could release one, now how to know if people are interested is another story, if they dont test the waters we may never know.

 

[StefanR5R]

Is there any reason that AMD Epyc 4584PX and EPYC 4484PX couldn't be 2x V-cache?

Neither the laws of physics nor the laws of man prohibit it.