Info TSMC, Samsung and IFS's Quarterly Financial Reports

[Tigerick]

I have decided to start a new thread discussing the financial report and release timings from 3 foundry service providers, namely TSMC, Samsung and late comer, Intel.

Times (2.5 years)	Cycle	Stage	Details
T - 30m	Design	Definition	Features / Performance / Power
T - 24m	Fab	A0 Tape-In
T - 15m	Fab	Power On
T - 12m	Post Silicon Validation	ES1 / Alpha	Board Bring Up & Early Val Alpha Validation
		ES2 / Beta	Beta Validation
		QS	QS Validation
	Customers Image Freeze	PRQ / PV	Prod Pilot & Test
T	HVM
T + 12m (3.5years)	Shipping

Above table are summarized from Intel Tech Tour regrading IC's development cycle. The same cycle should be applied to TSMC's cycle. The only thing I added is regarding after OEMs tape-out the design and enter stage of HVM. As you can see from the table below, OEMs are working closely with TSMC's timeline. As soon as TSMC announced start of HVM, OEMs will start production immediately. The reasons behind are beacuse OEMs are well aware of benefits of newer process node and they design their SoC/GPU to take advantages of PPA from newer node.






TSMC: King of Advanced Process

TSMC's 2024	Q1	Q2	Q3	Q4	Total based on Nodes
N7/N6	$3.59 b
N5/N4/N4P	$6.98 b
N3B/N3E	$1.7 b
Total based on Quarter	$12.27 b

TSMC's 2023 Process Node	Q1	Q2	Q3	Q4	Total based on Nodes	FY2022
N7/N6	$3.34 b	$3.61 b	$2.76 b	$3.34 b	$13.05 b	$20.49 b
N5/N4/N4P	$5.18 b	$4.7 b	$6.39 b	$6.87 b	$23.14 b	$19.73 b
N3B	NA	NA	$1.03 b	$2.94 b	$3.97 b	0
Total based on Quarter	$8.52 b	$8.31 b	$10.18 b	$13.15 b	$40.16 b	$40.22 b

Node	HVM's Date	OEM's First Shipment Date	Products
N4P	Q4 2022	Q4 2023	Qualcomm's SD 8 Gen 3
			Mediatek's Dimensity 9300
		2024	AMD's Zen5 and RDNA4 ?
			Intel's Battlemage
		Q3 2024	Qualcomm's SD X Elite
			AMD's Strix Point ?
		Q4 2024	AMD's Turin 128xZen5 ?
		Q1 2025	AMD's Kraken Point ?
N3B	Sept 2022	Q3 2023	Apple's A17 Pro
		Q4 2023	Apple's M3, M3 Pro & M3 Max
		Q4 2024	Intel's ArrowLake 8P+16E
			Intel's Lunar Lake
		Q4 2025	Intel's ArrowLake 8P+32E ?
		2025	Apple's M4, M4 Pro & M4 Max ?
N3E	Q4 2023	Q3 2024	Apple's A18 & A18 Pro
			AMD's Turin Dense 192xZen5c ?
		Q4 2024	nVidia's Blackwell ?
			Qualcomm's SD 8 Gen 4 ?
			Mediatek's Dimensity 9400 ?
		2025	AMD's Sarlak
			AMD's RDNA5
			Google's Tensor G5
N3P	H2 2024	Q3 2025	Apple's A19 Pro ?
		Q4 2025	Qualcomm's SD 8 Gen 5 ?
		2026	AMD's Venice/Zen6 16xZen6 CCD ?
			Intel's Celestial
			Tesla's FSD HWD 5.0
N2	Q4 2025	Q3 2026	Apple's A20 Pro ?
		Q4 2026	Intel's Nova Lake 16P+32E ?
		2027	AMD's Venice/Zen6c 32xZen6 CCD ?
N2P	H1 2026	Q1 2027	?
A16	H2 2026?	?	?

	Intel's Sapphire Rapids	AMD's Phoenix	AMD's Strix Point	Apple's M1 Max	Apple's M3 Max	Apple's M4 Max	nVidia's AD102	nVidia's GB202	nVidia's H100/H200	nVidia's B100
Date	Q1 2023	Q1 2023	Q3 2024	Q4 2021	Q4 2023	2025 ?	Q4 2022	Q4 2024 ?	Q4 2023	Q4 2024 ?
Process Node	Intel 7	N4	N4P	N5	N3B	N3B	4N	N3E	4N	N3E
Die Size	400 mm2	178 mm2	225 mm2	432 mm2	~ 531 mm2	?	609 mm2	?	814 mm2	?
Transistors	12 B	25 B	~ 32 B	57 B	92 B	?	76.3 B	?	80 B	?
Effective Density (MTs/mm2)	30	140.4		131.9	173.3	?	125.3	?	98.3	?
+% vs M3 Max	x 5.78	+ 23.4%		+ 31.9%			+ 38.3%		+ 76.3%

Samsung LSI + Foundry: 2nd Player in Foundry Business

Samsung Device Solution's 2023 Revenue (Tri KRW)	Q1	Q2	Q3	Q4	Total	FY2022
Device Solutions	$13.73	$14.73	$16.44	$21.69		$98.46
- Memory	$8.92	$8.97	$10.53	$15.71		$68.53
System LSI + Foundry	$4.81	$5.76	$5.91	$5.98	$22.46	$29.93
Convert to USD	$3.58 b	$4.29 b	$4.4 b	$4.5 b	$16.77 b	$22.53 b

IFS: New Challenger to become No.2

IFS's 2024	Q1	Q2	Q3	Q4	Total - e $16b
Revenue
Operating Income

IFS's 2023 Total Revenue	Q1	Q2	Q3	Q4	Total
Revenue	$118 m	$232 m	$311 m	$291 m	$952 m
Operating Income	- $140 m	- $143 m	- $86 m	- $113 m	- $482 m

Don't be fool by above financial data, according to Intel's CFO:-

Intel’s internal business units will now have a customer-supplier relationship with the manufacturing business, Chief Financial Officer David Zinsner said on an investor call.

Based on that model, Intel will be the second largest foundry next year with manufacturing revenue of more than $20 billion, he said.

Node	MR's Date	Availability	CPU	Shipping
Intel 4	Q4 2022		Meteor Lake	Q4 2023
Intel 3	H2 2023		Granite Rapids	2024 ?
			Sierra Forest	H1 2024 ?
Intel 20A	H1 2024	Late 2024 Products	Arrow Lake 6P	Q1 2025 ?
Intel 18A	H2 2024	Late 2025 Products	Clearwater Forest	2025 ?
			Panther Lake	Q4 2025 ?
			Diamond Rapids	2026 ?
Intel 18A-P	2025		Nova Lake 8P+16E ?	Q4 2026 ?
Intel 14A	Late 2026 Risk	?
Intel 14A-E	2027 Risk	?

 

[DrMrLordX]

@Tigerick

That's just Intel selling wafers to itself though.

 

[capricornsunvoyager2]

When is Samsung going to ship a product using it's 3nm process node?

That's their opportunity to make a comeback.

 

[eek2121]

@Tigerick

That's just Intel selling wafers to itself though.

Not “just”, but yes, Intel is including themselves. I don’t personally see anything wrong with that since Intel could just as easily NOT use IFS.

IFS actually has quite a few customers, but half of them you would never know used IFS. They don’t really have any big names (doing major projects)

EDIT: AMD could silently start using IFS and we’d never know!

 

[Ajay]

When is Samsung going to ship a product using it's 3nm process node?

That's their opportunity to make a comeback.

IIRC their N3 GA process (stacked or fork sheets?) was supposed to be ready this year. I don't know where that stands right now, but no news is bad news in this case.

 

[Doug S]

IIRC their N3 GA process (stacked or fork sheets?) was supposed to be ready this year. I don't know where that stands right now, but no news is bad news in this case.

Yeah it is telling that Samsung recently announced plans for 1.4nm but still no one seems to know of any real world chips using their 3nm. Maybe there are some cryptominers or other publicity shy companies with modest needs that could tolerate low yields? Until someone gets their hands on some type of ARM design coming out of Samsung's fab that could be compared with same/similar designs on various TSMC nodes nothing can be known about its true performance. Even if it turns out to perform better than N3E that won't matter if they are still having problems getting acceptable yields.

Because other than for Samsung's own use no one is going to be interested in capacity that yields terribly, absent some sort of "known good die" deal like Apple's with TSMC for N3B.

 

[DrMrLordX]

Not “just”, but yes, Intel is including themselves. I don’t personally see anything wrong with that since Intel could just as easily NOT use IFS.

IFS actually has quite a few customers, but half of them you would never know used IFS. They don’t really have any big names (doing major projects)

EDIT: AMD could silently start using IFS and we’d never know!

When will Intel start showing revenue for its 18a contracts? Because the revenue you're seeing now is 22FFL and Intel 16 (presumably, unless they're showing early revenue from Intel 3 contracts), and it looks like most of the major players that want to use Intel are waiting for 18a.

If there's a major jump in IFS revenue soon-ish before Intel can start reporting 18a revenue, it's a safe bet that near-100% of that increased revenue is Intel paying itself for wafers.

 

[Ajay]

Yeah it is telling that Samsung recently announced plans for 1.4nm but still no one seems to know of any real world chips using their 3nm. Maybe there are some cryptominers or other publicity shy companies with modest needs that could tolerate low yields? Until someone gets their hands on some type of ARM design coming out of Samsung's fab that could be compared with same/similar designs on various TSMC nodes nothing can be known about its true performance. Even if it turns out to perform better than N3E that won't matter if they are still having problems getting acceptable yields.

Because other than for Samsung's own use no one is going to be interested in capacity that yields terribly, absent some sort of "known good die" deal like Apple's with TSMC for N3B.

I kind of find it frustrating is a sense. We 'could' have a three horse race between TSMC, SS and IFS, which would be great for diversifying the semiconductor supply chain. But, SS seems to keep dropping the ball and IFS needs to be spun off before it will really be tested as a pure fab.

 

[Mopetar]

Not “just”, but yes, Intel is including themselves. I don’t personally see anything wrong with that since Intel could just as easily NOT use IFS.

I don't think that could be easily accomplished at all. They'd have to split wafers between multiple other fabs and compete against Apple for capacity on TSMCs bleeding edge node.

 

[Tigerick]

There is rumor that TSMC is getting Intel's orders of N3 process (finally). By the end of 2024, the total order would amount US$4 billion and in 2025, Intel would order up to $10 billion of wafer. TSMC would prepare 15,000 wafer per month by the end of 2024 and ramp up to 30,000 wafer per month in 2025.

This news is from reputable financial analyst, you guys should hear English version in the future. Of course, amount could change but with Lunar Lake and ArrowLake 8P coming end of next year, it is pretty sure that Intel will order wafer from TSMC N3B process for above mentioned CPUs...

Here is Eng version from SmartKarma: https://www.smartkarma.com/insights...intel-by-accelerating-3nm-outsourcing-to-tsmc

 

[Tigerick]

Guys, I have updated the front page with the information of IC's development cycle. Plus, the fun table which would be product release timing with each TSMC's newer process node. I thought it would be difficult to compile but no, it seems logical to list all the known leaks based on the HVM date of TSMC.

When TSMC's start HVM of new process, all OEMs will lineup to the production queue ASAP. However, we will see how the future advanced nodes will affect the release timings cause newer High-NA EUV will be even limited in quantity...

 

[DrMrLordX]

By the end of 2024, the total order would amount US$4 billion and in 2025, Intel would order up to $10 billion of wafer.

Just so we're clear, Intel supposedly paid up-front for this (and then delayed taking the wafers, allegedly). Are they paying out additional cash for these wafers, or is this just part of the allocation for which they prepaid some time ago?

 

[Doug S]

Guys, I have updated the front page with the information of IC's development cycle. Plus, the fun table which would be product release timing with each TSMC's newer process node. I thought it would be difficult to compile but no, it seems logical to list all the known leaks based on the HVM date of TSMC.

When TSMC's start HVM of new process, all OEMs will lineup to the production queue ASAP. However, we will see how the future advanced nodes will affect the release timings cause newer High-NA EUV will be even limited in quantity...

They will only be using high NA for a few critical layers so having only a few high NA machines shouldn't be a roadblock, at least not for the first process that uses high NA. If it sweeps through the layers as quickly as EUV though I agree it could become a bottleneck. Especially since this time three companies will be vying for production level deliveries - with "EUV 1.0" Intel was sitting on the sidelines.

 

[Doug S]

Just so we're clear, Intel supposedly paid up-front for this (and then delayed taking the wafers, allegedly). Are they paying out additional cash for these wafers, or is this just part of the allocation for which they prepaid some time ago?

You could check their filings. Any prepayment of that size for undelivered wafers would show up as an asset on their balance sheet.

 

[Tigerick]

TSMC's N3B process Explained

• There is a lot of misinformation regarding N3B process by TSMC. First please read about N3B vs N3E in Apple thread that I explained here. Intel and Apple are well-aware of the advantage of N3B process; and what you are seeing is the first iteration of N3B. That's why I am pretty confident that Apple's M4 series will continue using N3B, same as ArrowLake 8P+32E version. In fact, both SoC's might offer similar die size as current one due to utilization of 25 EUV layers.
• Semiwiki likes to list the theoretical numbers of each process that provided by TSMC, Samsung or Intel. It seems pointless cause SoC contains combination of logic and SRAM with different memory interfaces. We should focus on real SoC that build by each process as listed in the table above. M3 Max with 173.3 MTs/mm2 seems to offer improvement of 31.9% compared to M1 Max. Remember this is the first model that build on N3B, let's wait and see how much M4 Max's transistors will provide...
• Even AD102 and H100/H200 using same process node but because of different memory interfaces, the effective density of H200 is far lower than AD102. The fun part is I have the information of Sapphire Rapids' die size and transistor counts. Holy mother, no doubt Intel 7 is older process compared to 4N, but the H100's density improvement is more than 3 times of Intel 7. Now you all know why Intel does not publish transistor counts of Alder Lake onwards...
• That's the issue faced by IFS, internally Intel could adjust the density of transistor to hit yield and clock speed they needed by sacrifice die area. This is not going to work with other OEMs, die size is most critical numbers they care about...
• As for yield issue, CEO of TSMC has addressed in Q3 2023's financial seminar:- "N3 is already in volume production with good yield and we are seeing a strong ramp in the second half of this year, supported by both HPC and smartphone applications"
• Here is another interesting article regarding N3B vs High NA (most likely used by N2) by SemiAnalysis. N3B clearly has pretty of headroom ahead. However, TSMC has to downplay it a bit due to pushing of N3E process; that's what CC Wei said about N3E: "N3E will leverage the strong foundation of N3 to further extend our N3 family with enhanced performance, power and yield and provide complete platform support for both HPC and smartphone applications. " No word on the logic density cause N3B clearly offer better logic density compared to N3E

 

[Tigerick]

	Q3 2023/24/25	Q4 2023/24/25	Quarterly Revenue	Wafers Per Q	Wafer Price
N3B	A17 Pro		$1.03 b	45000	$22,889
		+ M3, M3 Pro, M3 Max	$2.94 b	~ 129,000	$22,889
	Q1 2024		?	?	$22,889
	Q2 2024		?	?	$22,889
	Arrow Lake 8P+16E, Lunar Lake		$2 b	90000	$22,222
	+ Arrow Lake 8P+32E		$1 b	45000	$22,222
N3E	13 EUVs		$900 m * 13 = $11.7 b	45000	$20,000

Hoho, I think I crack how TSMC's 3nm revenue being calculated with above table. The table is simple yet informative, let me explain: -

• Basic 101: Each chip is manufactured by one EUV machine non-stop. The machine has to keep running 24/7 to produce the SoCs with 300mm wafer. Latest EUV machine can produce 15,000 wpm (ie 45,000 wafers per quarter). That's why after TSMC started HVM of new node, OEMs have to stockpiling the chips for around one year to get enough quantity to launch the products. FYI, one year period also includes cutting, testing, packaging and so on.
• The first SoC being produced is Apple's A17 Pro; first quarter revenue is $1.03b divided by 45,000 we get around $23,000 per wafer cost which inline with rumored $25,000. Next quarter, Apple has three more SoCs being produced at TSMC. TSMC should charge around $4 b but clearly the figure is far lower. A17 Pro and M3 are in high demand, that's why I suspect the machinery that produce M3 Pro and Max are not running at full capacity cause these two chips are not in high demand. We should see the revenue of N3B to hover around $3 b in the coming two quarters.
• I have mentioned about Intel's leaks on TSMC N3B above, this year Intel should have two chips being produced at TSMC's N3B thus $4 b business and $10 b for next year. Therefore, TSMC would provide three EUV machines for Intel next year. Last time I checked Intel has more than 10 EUV machines thus it is not related to factory limitation, it is just because of IFS's incapability to produce high end chips.
• By Q3 this year, we should see exponential growth of TSMC's 3nm revenue due to N3E process. Based on leaks, each wafer should cost around $20,000. Each quarter should contribute $900m per chip. So far I have listed 13 upcoming chips that are being produced at TSMC. Blackwell has rumored to have 5 different dies, thus should contribute $4.5 b per quarter, really big volumes. RDNA5 however only need one machinery due to chiplet design.
• That's why I expect TSMC's 3nm revenue will shoot from current $3b to more then $10b per quarter by end of this year. No wonder TSMC is confident their revenue will increase 25% this year and they have limited high end EUV machines for 3nm process.

 

[Ajay]

	Q3 2023/24/25	Q4 2023/24/25	Quarterly Revenue	Wafers Per Q	Wafer Price
N3B	A17 Pro		$1.03 b	45000	$22,889
		+ M3, M3 Pro, M3 Max	$2.94 b	~ 129,000	$22,889
	Q1 2024		?	?	$22,889
	Q2 2024		?	?	$22,889
	Arrow Lake 8P+16E, Lunar Lake		$2 b	90000	$22,222
	+ Arrow Lake 8P+32E		$1 b	45000	$22,222
N3E	13 EUVs		$900 m * 13 = $11.7 b	45000	$20,000

Hoho, I think I crack how TSMC's 3nm revenue being calculated with above table. The table is simple yet informative, let me explain: -

• Basic 101: Each chip is manufactured by one EUV machine non-stop. The machine has to keep running 24/7 to produce the SoCs with 300mm wafer. Latest EUV machine can produce 15,000 wpm (ie 45,000 wafers per quarter). That's why after TSMC started HVM of new node, OEMs have to stockpiling the chips for around one year to get enough quantity to launch the products. FYI, one year period also includes cutting, testing, packaging and so on.
• The first SoC being produced is Apple's A17 Pro; first quarter revenue is $1.03b divided by 45,000 we get around $23,000 per wafer cost which inline with rumored $25,000. Next quarter, Apple has three more SoCs being produced at TSMC. TSMC should charge around $4 b but clearly the figure is far lower. A17 Pro and M3 are in high demand, that's why I suspect the machinery that produce M3 Pro and Max are not running at full capacity cause these two chips are not in high demand. We should see the revenue of N3B to hover around $3 b in the coming two quarters.
• I have mentioned about Intel's leaks on TSMC N3B above, this year Intel should have two chips being produced at TSMC's N3B thus $4 b business and $10 b for next year. Thus TSMC will provide three EUV machines for Intel next year. Last time I checked Intel has more than 10 EUV machines thus it is not related to factory limitation, it is just because of IFS's incapability to produce high end chips.
• By Q3 this year, we should see exponential growth of TSMC's 3nm revenue due to N3E process. Based on leaks, each wafer should cost around $20,000. Each quarter should contribute $900m per chip. So far I have listed 13 upcoming chips that are being produced at TSMC. Blackwell has rumored to have 5 different dies, thus should contribute $4.5 b per quarter, really big volumes. RDNA5 however only need one machinery due to chiplet design.
• That's why I expect TSMC's 3nm revenue will shoot from current $3b to more then $10b per quarter by end of this year. No wonder TSMC is confident their revenue will increase 25% this year and they have limited high end EUV machines for 3nm process.

Apple isn’t paying for wafers for N3B. They are paying per good known dice. So, those numbers don’t make sense to me.

 

[Doug S]

There's no way if N2+BSPDN enters mass production in H1 2026 that it isn't being used for Apple's chips that fall. They will not use the non BSPDN version - that initial N2 also does not do FinFlex.

 

[Tigerick]

There's no way if N2+BSPDN enters mass production in H1 2026 that it isn't being used for Apple's chips that fall. They will not use the non BSPDN version - that initial N2 also does not do FinFlex.

You should at least read the latest transcript from TSMC's Q4 financial :-

N2 with backside power rail will be available in the second half of 2025 to customers with production in 2026.

Production means HVM in 2026, TSMC don't mention exact timeframe thus it is possible they would start HVM at H2 2026, my timing is based on Ian's interview with TSMC which they mentioned BSP will come half a year later. No matter what, OEMs will only begin shipping N2+BSPDN SoCs in 2027....

 

[Doug S]

You should at least read the latest transcript from TSMC's Q4 financial :-



Production means HVM in 2026, TSMC don't mention exact timeframe thus it is possible they would start HVM at H2 2026, my timing is based on Ian's interview with TSMC which they mentioned BSP will come half a year later. No matter what, OEMs will only begin shipping N2+BSPDN SoCs in 2027....

So your reading of "available in the second half of 2025 to customers with production in 2026" is that they can't get any products with it out the door until 2027? OK, but I think you are the only one who reads it like that.

 

[Tigerick]

I have updated Samsung Foundry's 2023 financial report: -

• FY2023's revenue has dropped from $22.5 b to $16.8 b. You would think being the first to offer SF3E process, the revenue would increase but no.
• As Samsung said: "We expect the foundry market to return to 2022 levels thanks to the recoveries in smartphone and PC demand. We are committed to increasing orders from applications in high-growth areas, such as AI accelerators, while focusing on mass production of 3-nanometer products based on the 2nd generation process as well as on the development of the 2-nanometer process."
• Samsung should begin HVM of SF3 process this year and they expect this year's revenue to hit 2022 level, ie $22 billion. The revenue gap between SF and TSMC will be widen; I am comparing whole LSI+Foundry versus TSMC's advanced process.
• IFS: Based on $20 b figures from CFO, this year IFS should be making $16b after deducting $4b from TSMC. Next year, the revenue should drop to $10b. IFS really needs external clients in order to earn better. However, if IFS cannot serve internal BU, then why the hell other OEMs would order up???

 

[FlameTail]

I have updated Samsung Foundry's 2023 financial report: -

• FY2023's revenue has dropped from $22.5 b to $16.8 b. You would think being the first to offer SF3E process, the revenue would increase but no.

Well, considering SF3E was used to make some obscure cryptominers...

• As Samsung said: "We expect the foundry market to return to 2022 levels thanks to the recoveries in smartphone and PC demand. We are committed to increasing orders from applications in high-growth areas, such as AI accelerators, while focusing on mass production of 3-nanometer products based on the 2nd generation process as well as on the development of the 2-nanometer process."
• Samsung should begin HVM of SF3

Yeah. Next gen Exynos 2500 will use SF3.

 

[Tigerick]

Tesla's next gen FSD SoC going to be manufactured by TSMC's N3P process. N3P is more like refined version of N3E with 4% density improvement @ similar pricing. Thus, all big OEMs will migrate to N3P asap to take advantage of it. Tesla FSD's HWD 5.0 would be among the first NTO for N3P process.

According to article, Tesla could become No.7 revenue contributor to TSMC in the future.

Source: MoneyDJ (Chinese)

PS: The article also mentioned Tesla has decided to say goodbye to Samsung Foundry, another story of "Been there, done that."

 

[Markfw]

AMD is not even in the top 7 at TSMC ? That sure surprises me. I would have thought they were in the top 3 !

Edit: I just read the article, I cannot see where it lists the top 7 anywhere. I see this though "...<snip> In addition to MediaTek (2454), AMD, NVIDIA, Qualcomm, INTEL and other customers <snip>...."

 

[Tigerick]

AMD is not even in the top 7 at TSMC ? That sure surprises me. I would have thought they were in the top 3 !

Edit: I just read the article, I cannot see where it lists the top 7 anywhere. I see this though "...<snip> In addition to MediaTek (2454), AMD, NVIDIA, Qualcomm, INTEL and other customers <snip>...."

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money.udn.com

Here is the source, yeah AMD is not listed. Anyhow the information is for this year, AMD should have more tape out for 3nm which contribute more.