Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[igor_kavinski]

PROM21 will have a long life yes.

I suppose the OEMs love that as it means less engineering/validation work for them. Whatever work they have done till Zen 5 launch and whatever lessons they learned after launch, they can now sit back and print money, at least on the chipset side.

 

[adroc_thurston]

I suppose the OEMs love that as it means less engineering/validation work for them. Whatever work they have done till Zen 5 launch and whatever lessons they learned after launch, they can now sit back and print money, at least on the chipset side.

Eh there certainly will be new mobos but yeah.

 

[Det0x]

Eh there certainly will be new mobos but yeah.

We are already seeing that on Zen4

Current 1DPC motherboards are having a much easier time reaching 8000MT/s and above while 2DPC generally seems to stop at ~7400-7600MT/s (if you require full stability)
Next generation boards will have a increased focus on memory traces for higher speeds

Pretty sure X670E GENE is having a boom atm

 

[adroc_thurston]

Next generation boards will have a increased focus on memory traces for higher speeds

No that's an inherent DDR5 limitation.
DDR6 doesn't support 2DPC at all.

 

[Det0x]

No that's an inherent DDR5 limitation.

What is ?
Currently there is a motherboard limitation for high memory speeds on the AM5 socket
(such as nonworking multipliers above 80(40) on the last 3 AGESA's)

Come Zen5 release you can bet your behind that we get a new "X770E" AM5 chipset with support for higher memory speeds as one of the major selling points over X670E

 

[igor_kavinski]

DDR6 doesn't support 2DPC at all.

So it will be quad channel? Coz I don't see why they will go from four dimms to just two universally.

 

[adroc_thurston]

What is ?

DDR5 is inherently slower with longer traces required for 2DPC fanouts.

So it will be quad channel?

No.

Coz I don't see why they will go from four dimms to just two universally

DIMMs are already way denser with 24Gbit dies so not a problem really.

 

[Det0x]

DDR5 is inherently slower with longer traces required for 2DPC fanouts.

You are missing the forest for the trees

Noone is arguing that a 2DPC layout will match the speeds a 1DPC layout can achieve, on average
But that does not have any bearing on one of the major selling points for the next generation "X770E" AM5 motherboards will use over current X670E/B650E, memoryspeed going forward will get much more focus

 

[adroc_thurston]

But that does not have any bearing on one of the major selling points for the next generation "X770E" AM5 motherboards will use over current X670E/B650E, memoryspeed going forward will get much more focus

Ughhhh alright whatever floats your boat.

(You don't pump DDR clock on Zen5, it doesn't do anything. At all)

 

[Det0x]

nevermind then :=)
Only a few more months

 

[adroc_thurston]

nevermind then :=)
Only a few more months

Yes, going zoom zoom on your DDR kit will be a lot more useful on Zen6.
But not on Granite Ridge.

 

[A///]

We are already seeing that on Zen4

usb4 something right?

 

[soresu]

Speaking only for myself and a minority of others, some of us need a LOT of cores, and fast ones, but not as much PCIE lanes and other functionality of TR or EPYC, and we don't want to pay for it. There is a market, not sure the total size.

Mmmhmmm - in the words of the great Johnny 5....

 

[Ajay]

@igor_kavinski So it will be quad channel? Coz I don't see why they will go from four dimms to just two universally.

So, problem number one:

From Altium's website (PCB design software) : DDR5 and DDR6 take the top-end DDR4 data rate and double it again (and another doubling in DDR6) by making buses faster, rather than wider. You’re still dealing with DDR4 routing challenges in terms of laying out parallel single-ended nets, but these channels are much shorter. Buses will also run fast enough that typical channels will usually be electrically long, so bit errors will be dominated by insertion losses along interconnects.

Having insertion loses from two DIMMS on the same channel would just ruin the signal that the IOD will see. The classic 'eye' shape we see in high speed signals would collapse and render the bit level indeterminant. The problem that I see is that with only 1DPC, the bus width will be halved, so even when running at twice the frequency, the data rate will not change. So, something else will need to be changed or , for example, a dual CCD Ryzen CPU will be bandwidth starved. A very large SLC on the IOD maybe?

Edited.

 

[adroc_thurston]

So it will be quad channel?

No.

I don't see why they will go from four dimms to just two universally.

Yes you will.
No one will ask and you shall accept that.

 

[Ajay]

No.

Yes you will.
No one will ask and you shall accept that.

Lol, I was quoting someone else - forum bug I guess. Mostly fixed with edit. Something is really screwed up.

 

[adroc_thurston]

Lol, I was quoting someone else - forum bug I guess. Mostly fixed with edit. Something is really screwed up.

Ah, sorry.
lol.

A very large SLC on the IOD maybe?

A small one (like 8MB) is enough.

 

[Ajay]

Ah, sorry.
lol.

A small one (like 8MB) is enough.

Geez, almost why bother?! Anway, curious to see how AMD will handle the DDR6 problem on DT. Server will be different (CLX everywhere I guess).

 

[maddie]

Possible reason if the rumor is true: https://www.hardwaretimes.com/intel...able-units-why-hyper-threading-is-going-away/

That looks a lot influenced by SoftMachines work & they were bought by Intel. One thread split among 2 cores.

 

[adroc_thurston]

Geez, almost why bother

Worked for M1™.

Server will be different

No lol.

CLX everywhere I guess)

 

[Ajay]

Worked for M1™.

Hmm, maybe the base SoC. Pro and Max were 24/48 MB. Lots of L2$ as well. Anyway - still dual channel so the math still works out - (duh, yet again I need to return my uni degree).

 

[adroc_thurston]

Pro and Max were 24/48 MB

Lots and lots of GPU in there.

Lots of L2$ as well

AMD has a lot of L3 instead.

 

[SpudLobby]

https://twitter.com/x/status/1693975687919800555

https://twitter.com/x/status/1694293526157344975

Well, if this is true, and it looks legit for now - even less competition for AMD in the performance market with Zen 5. 1600 @ 3.4GHz is higher than the X3 but barely. TBD on power. There's also further delay apparently.

Then we've got this. Almost certainly due to anticipated lower demand IMHO, at least at the prices they can afford to charge - BOM is indeed going to rise now that Intel's ramping i4/i3, using TSMC's leading nodes, etc.

https://twitter.com/dylan522p/status/1693981897309761657

It's AMD's to lose to some extent with Zen 5 in mobile client parts.

 

[SpudLobby]

Lots and lots of GPU in there.

AMD has a lot of L3 instead.

Yeah that's right. 8MB of LLC is definitely to reduce some system power consumption consumption from hitting DRAM and boost BW for a smaller GPU.

 

[Doug S]

https://twitter.com/x/status/1693975687919800555

https://twitter.com/x/status/1694293526157344975

Well, if this is true, and it looks legit for now - even less competition for AMD in the performance market with Zen 5. 1600 @ 3.4GHz is higher than the X3 but barely. TBD on power. There's also further delay apparently.

Then we've got this. Almost certainly due to anticipated lower demand IMHO, at least at the prices they can afford to charge - BOM is indeed going to rise now that Intel's ramping i4/i3, using TSMC's leading nodes, etc.

https://twitter.com/dylan522p/status/1693981897309761657

It's AMD's to lose to some extent with Zen 5 in mobile client parts.

I'm pretty skeptical of that. That would be worse than the original Nuvia was projected to be. Though I guess if anyone could take their work and screw it up, it would be Qualcomm!