Thats not to what I am pointing .No.
But they're a tiny bit lower.
Not when you know how Turin runs.
Yea.So you are still sticking to your 32%+ IPC on average, for the core itself?
Mobile like STX will still boost to upper 4s/lower 5s GHz.But IPC will be very high even in low power thermal envelopes-low clocks.
I guess I'll come out and say what standard Venice probably looks like now.
6 AID's, each with 4 2.5D stacked 8 core CCD's, each AID connected to each other with silicon bridges.
And finally 6 IO dies, connected to the outside of each AID with fanouts, each IO die with 2 memory channels and a bunch of PCIE/CXL lanes.
192 cores, huge fully unified MALL, along with so much room for all sorts of uncore accel and other server stuff.
Venice gets rid of EPYC's last weaknesses, for a huge fee, of course. Many will probably stick with Turin initially but Venice will become a huge stick of doom over time.
Zen 5 is looking better and better as we are closing on the release date. Bring on the big chungus cores from AMD, finally! They were so frugal vs the competition in the recent Zen gens - now we'll finally see how much more performance they can extract by using similar resources as intel's cores.No.
But they're a tiny bit lower.
It's bigger than what Intel ships until Lion Cove.They were so frugal vs the competition in the recent Zen gens - now we'll finally see how much more performance they can extract by using similar resources as intel's cores.
No, its core-IP/CCD codenames.No, they're core/cache codenames.
Zen 5 16c CCX is a logical step to eliminate a previous gen's cut corner. Just like Zen 2 got 2*CCX and Zen 3 joined them together. Zen 4c got 2*CCX and Zen 5(c?) got joined them together.What is interesting though is the native 16C CCX. Clark had this in mind during the 2021 interview with AT looks like.
Also Z6 has a 32C CCX
what does that mean? That zen 5 7950x replacement will have 16 core, but only single compute die?What is interesting though is the native 16C CCX. Clark had this in mind during the 2021 interview with AT looks like.
Zen 5 standard would be N4 with 8 cores per CCDNo, its core-IP/CCD codenames.
Zen 5 16c CCX is a logical step to eliminate a previous gen's cut corner. Just like Zen 2 got 2*CCX and Zen 3 joined them together. Zen 4c got 2*CCX and Zen 5(c?) got joined them together.
The 32c CCX is a surprise tho.
what does that mean? That zen 5 7950x replacement will have 16 core, but only single compute die?
The internal AMD slide is the one that says that not MLIDSo MLID seems to think that Zen 5 will bring Zen 4-like IPC , even though the changes are way more massive than Zen 2 -> Zen 3.
What is interesting though is the native 16C CCX. Clark had this in mind during the 2021 interview with AT looks like.
Also Z6 has a 32C CCX
CCD's don't need SoIC-X, something akin to Foveros is fine.Mi300 is 4 base dies with 3x 3D Hybrid Bond stacked CCDs.
First, I don't know what you mean 2.5D stacked, I am pretty sure it will be 3D stacked, since Venice will be 2 years after Mi300.
4 tile is possible, but it has to be more cores than Turin, so you just inflate the size of each tile.Second the size of this would be probably bigger than Mi300 by factor of 1.75x, to 2x and Mi300 is already quite big. 24 CCDs that you are suggesting vs. max of 12 CCDs for Mi300. It is possible, but I think not very likely.
I think 4 base die make a much nicer group for interconnecting them all, and you may be right with going up to 4 CCDs per AID. For 16 CCDs.
Maybe the server standard CCD moves to 16 cores with Zen6, but I really doubt it.The CCDs will have 16 and 32 cores, so would be 256 to 512 cores.
The fanout introduced with RDNA3 is nice and cheap, and works well for this purpose. Si bridge would be overkill.If they are already doing silicon bridges, it makes no sense to also do fanout, if you can as well do another set of silicon bridges to IO dies.
So, I think 4 IO dies, each one connecting to 3-4 memory channels
Cache isn't magic, 8 cores is basically the limit for a high performance L3.I don't think there will be any more 8 core CCDs for server by the time Zen 6 comes around.
Venice is built for the guys who care about TCO and perf density and nothing else.If they were thinking it was feasible to do Navi 4c in 2024 for ~ $1500, I don't think the cost will be a big barrier to entry for Venice server CPU. a year later.
Others have addressed that, read up in the thread. It's not my fault that MLID has no IQ capacity to interpret the data he has been fed to.The internal AMD slide is the one that says that not MLID
it's just one person making claims without anything to back them up. I would trust an AMD slide over this.Others have addressed that
Phoenix has 5.1GHz turbo. If Strix Point will manage 4.8-4.9Ghz, I think 4-6% regression is not a problem.Mobile like STX will still boost to upper 4s/lower 5s GHz.
Well that AMD slide says 15+%. That is, 15% is a baseline.
You do know what + sign means, right? If you think that all those MASSIVE core changes will get Zen 4 like IPC increases, then I don't know what to tell you. I suggest you check all the previous MASSSIVE Zen sandbags AMD did in the past, maybe that will give you some clues.it's just one person making claims without anything to back them up. I would trust an AMD slide over this.
it's possible AMD is sandbagging but the point is that 10-15% isn't just some number MLID pulled out of thin air like you were trying to say, it's from the slides. MLID actually said that he expects it to be in the 15-25% range.You do know what + sign means, right? If you think that all those MASSIVE core changes will get Zen 4 like IPC increases, then I don't know what to tell you. I suggest you check all the previous MASSSIVE Zen sandbags AMD did in the past, maybe that will give you some clues.
edit: In case you missed it, AMD's play on the + or > sign is comical : http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...ranite-ridge-ryzen-8000.2607350/post-41081283
How >15% actually DOUBLES to 29%. But hey, keep believing the 10-15% numbers if you like. Many people were stating the same thing when first Zen 4 tease came out (the one with 15+% ST performance increase).
Wow, such a narrow range for such a great expert! I'm in awe lmaoit's possible AMD is sandbagging but the point is that 10-15% isn't just some number MLID pulled out of thin air like you were trying to say it's from the slides. MLID actually said that he expects it to be in the 15-25% range.
lol what? I am not defending anyone. I am aware that most of MLID leaks are usually BS but you are blaming him for a number in an AMD slide that he even said it will likely be higher in that same video.Wow, such a narrow range for such a great expert! I'm in awe lmao
The dude had so many failed predictions it's not even funny. You are defending a sensationalist click baiter who cannot deduce simple things even when he is spoon fed such valuable information.
The slide clearly deals with CCX (Core Complex) not CCD (Core Complex Die).Zen 5 standard would be N4 with 8 cores per CCD
Zen 5c N3 with 16 cores per CCD
Zen 6 standard N3 with 16 cores per CCD
Zen 6c N2 with 32 cores per CCD