So big.LITTLE, and thus Zen 5P & 5E on DT, after all.no.
AMD isn't spamming dense in client DT.
No, they'll have an actual LITTLE to do the low-power island thing
No.So big.LITTLE, and thus Zen 5P & 5E on DT, after all.
No.Like I said previously, it was bound to happen, but AMD was just a little late the party after everyone else in the business already did it (Apple, Qualcomm, Intel, ...).
NO.Now we'll just have to see what AM5 Zen5 SKUs there will be, e.g.:
* 2x8P
* 1x16P
* 2x16P
* 8P+16E
* 2x16E
* 8P+2x16E
NO. Just no.It's still unclear if the 16C CCX:es will only be for E or P cores for Zen5. I.e. if there'll be any 16P CCX, or only 8P CCX and 16E CCX.
pretty sure its supposed to be AM5From a platform perspective are we expecting new 770/750 chipsets?
I am not sure if there is any point...From a platform perspective are we expecting new 770/750 chipsets?
No.From a platform perspective are we expecting new 770/750 chipsets?
Looking at this again it, vs Z4
Does not seem terribly bloated, would have indeed seems akin to the Z2 -> Z3 evolution. The unknowns however do seem like the kind of big ticket items. I think the zero bubble conditional branch could be tied to the "2 basic block fetch".
- +2 rename/dispatch
- +2 ALUs
- +1 LD/cycle
- 512b FP width
- 64B LD/ST queues
- 48K L1D
- OOO structures increased
- Usual generational architectural improvements scattered around
- New BP with larger BTBs -> zero bubble conditional branches sounded like the patent I listed before where a second BP scans the other conditional branch
- Decode width unknown, doubtful it is going to be beyond 6 wide if at all they even increase.
- uop cache unknown
- "2 basic block fetch"
--> Does this mean 2x fetch and decode blocks akin to Tremont?
Low Power core
However a major departure from Zen 3/4 series are the unified schedulers for INT and FP back to Zen 2 style. Would be interesting to see latencies with Zen 5.
- Probably the low power core option is not having 512b FP pipes or 64B LD/ST queues (they mentioned FP 512 variants, which would mean 512 pipes and data structures not standard across all core)
- Denser node/efficiency optimized libs as usual
- Cache reduction as usual
Ifthe 2x basic block fetch is akin to what I described, they could clock gate the second fetch block aggressively for mobile
Thoughts are this looks 3 years old and is probably a bit out of date.I just noticed that in the slide below, for Nirvana it says "Low power core option". Notice that this is different naming compared to for Persephone where it says "Dense option".
Any thoughts on this?
Well sure but how many chipset gens were AM4? (3 or 4).pretty sure its supposed to be AM5
I am likely going to get Zen5, so wondering if there were going to be new chipsets/motherboards, like previous generations on AM4. Currently still on an AM4 socket MB. If not I may try to just grab a current AM5 MB on the blackfriday deals.No.
Why?
Sure but we had x370(2017),x470(2018),x570(2019), was not really sure if we were due for an 770 aligned with zen5 as last socket debut had consecutive years of new chipsets.Zen3 had none of.
I don't remember exactly what the changes were, but for example, PCIE 2, PCIE3, and PCIE4 . At least 3 and 4 were in these. at first, you needed a new chipset for a new Zen version, like 570 for Zen 3, but eventually I think all 3 now support all 1,2,3 generations. So at the time they were needed but after bios updates, its just feature set. Zen 4 to Zen 5 brings nothing that I am aware of unless it supports PCIE 5.0.Sure but we had x370(2017),x470(2018),x570(2019), was not really sure if we were due for an 770 aligned with zen5 as last socket debut had consecutive years of new chipsets.
Thoughts are this looks 3 years old and is probably a bit out of date.
That being said, it'd be interesting to see if they did go for a different core design, seems to work well for Apple and their ridiculously efficient low power cores. Or we could see what Intel did with their new "Double E" or whatever they're calling it, the pair of E cores in Meteor lake that are on the I/O tile and tweaked to run at lower voltage.
Same thing, Promontory, became B550.x370(2017),x470(2018)
That's a Bixby aka cIOD.x570(2019)
No.No.
No.
NO.
NO. Just no.
The LITTLE in question is a Cat-core style sub 600mW thingy designed for 4c cluster low power operation.
What info.Nothing of what you write matches the info from AMD.
See previous posts with leaked slides.What info.
Their actual LITTLE isn't even public/on-roadmaps for now.
This isn't their LITTLE.See previous posts with leaked slides.
And your source for that info is what? Any link?This isn't their LITTLE.
It's not on the roadmaps for now.
Get more notoriety and you'll learn much the same.And your source for that info is what?
So as I assumed, you have no source. You’re just guessing.Get more notoriety and you'll learn much the same.
Yeah whatever floats your boat.So as I assumed, you have no source. You’re just guessing.