Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Goop_reformed]

Yeah.

Late March or April.

+32% ipc w/ -7% clock (400mhz, from 5.7ghz to 5.3ghz ) will yield 25% st uplift. Still hoping for more to be honest. You mentioned before zen 5 was designed to compete with arrow lake. Would you say amd have just done just that? Surely the arrow lake AMD have in mind is quite a tad faster than that appeared in the intel projection slide.

 

[DrMrLordX]

Dawg it was a Daytona issue.

Marketshare is irrelevant if you're forcing a price war against an IDM and tanking the margin.

On a more serious note, yeah, that is what is happening. Everytime someone says "oh but look at much Cascade Lake/Sapphire Rapids!" sold, you have to consider: at what price? Before AMD can eat Intel's market share, they'll have to eat their margins.

 

[adroc_thurston]

You mentioned before zen 5 was designed to compete with arrow lake

Yeah, 2024 was supposed to be a party.

Before AMD can eat Intel's market share, they'll have to eat their margins.

At least SPR has horrible cost structure.
In client Intel is still cheapo until Raptor Lake is out of circulation (which is quite some time away).

 

[H433x0n]

Yeah, 2024 was supposed to be a party.

If there’s a 25% 1T perf increase why wouldn’t it be a party?

 

[H433x0n]

+32% ipc w/ -7% clock (400mhz, from 5.7ghz to 5.3ghz ) will yield 25% st uplift. Still hoping for more to be honest.

That would be absolutely bonkers if it turned out that way. If I were looking to buy AMD I’d be really happy with that outcome.

What exactly were you expecting?

 

[adroc_thurston]

If there’s a 25% 1T perf increase why wouldn’t it be a party

Lisa's gonna take my kidneys away.

That would be absolutely bonkers if it turned out that way.

25% 1t is kinda the bare minimum expectation for an AMD tock.

 

[randomhero]

What about vcache chips? I have feeling that we will see more gains than with previous Zen gens. These wide cores demand more bandwidth.

 

[randomhero]

Edit and off topic: Boy what will Zen6 with new package do in this regard

 

[adroc_thurston]

What about vcache chips

They're the same.

I have feeling that we will see more gains than with previous Zen gens

Kinda the opposite, Zen5 is better at coping with bad memory setups.

Boy what will Zen6 with new package do in this regard

Nothing.
It's just an efficiency and design reuse play.
They're using the cheapest 2.5D option available for client.

 

[H433x0n]

Lisa's gonna take my kidneys away.

Not sure what is meant by this, if it’s in reference to the stock / business fundamentals I don’t see anything in 2024 that would spell doom but I don’t have any special insight into the company.

25% 1t is kinda the bare minimum expectation for an AMD tock.

ARL-S will allegedly have an uncharacteristically weak 1T perf increase. So if there was ever a time to miss the 30% 1T target it’d be in 2024.

 

[Timorous]

Not sure what is meant by this, if it’s in reference to the stock / business fundamentals I don’t see anything in 2024 that would spell doom but I don’t have any special insight into the company

It means he thinks it will be very expensive.

 

[H433x0n]

It means he thinks it will be very expensive.

I don’t think that’s it. Zen 5 shouldn’t be that much more expensive than Zen 4.

 

[Joe NYC]

Marketshare is irrelevant if you're forcing a price war against an IDM and tanking the margin.

That's like advocating a unilateral disarmament in place of a threat of Mutual Assured Destruction.

A sure way to lose - as AMD has lost - 2/3 of the client market share.

 

[Timorous]

I don’t think that’s it. Zen 5 shouldn’t be that much more expensive than Zen 4.

More expensive node, larger die (probably, zen 4 CCD is tiny) and a potentially materially relevant performance advantage all point to AMD trying to hike prices again like they did with Zen 2 to Zen 3.

EDIT: OTOH cheaper motherboard prices and cheaper ram might offset a CPU cost increase for a new builder vs Zen 4 when it was launched. Depends how much AMD hike it if they do.

 

[inf64]

Not sure if this has already been posted: https://chipsandcheese.com/2023/09/06/hot-chips-2023-characterizing-gaming-workloads-on-zen-4/



"Both gaming workloads are overwhelmingly frontend bound. They’re significantly backend bound as well, and lose further throughput from bad speculation. Useful work occupies a relatively minor proportion of available pipeline slots, explaining the low IPC."

Zen 5 main design goals:


Looks like Zen 5 will address the main bottlenecks in Zen 4, at least when gaming is concerned. Fun times for Arrow Lake

 

[eek2121]

For clocks and performance, not IPC.

Increased IPC increases power consumption.

March or April seems optimistic to me. AMD never specified the exact half year, they just said 2024. This is usually an indication for a H2 launch rather than a H1 launch. I don't think we are getting Zen 5 in H1 of 2024.

AMD announces new mobile parts every January, so we should get mobile Zen 5 at minimum.

Intel is dropping Raptor Lake Refresh now and Arrow Lake H2 2024. If Zen 5 is a zinger, AMD will want to release it ASAP, that way they can have at least a year of market leadership.

Yeah, I wouldn’t bet against an H1 2024 release.

As I have also stated, I also would not bet against a larger than expected IPC jump, even absent the recent slide “leak”. There are too many indicators I have seen over the past few months that indicate we will see bigger gains.

Finally, you guys either need to sober up when on these forums or take a moment to re-read posts. You guys are laying into @adroc_thurston like crazy to the point you go on the attack for nothing. I am just as critical of someone with no credibility showing up and making grandiose claims as the next person, but this IS a discussion and speculation thread, and the results WILL bear themselves out eventually. If he is right, he will be right, if he is wrong, he will be wrong.

 

[yuri69]

"Both gaming workloads are overwhelmingly frontend bound. They’re significantly backend bound as well, and lose further throughput from bad speculation. Useful work occupies a relatively minor proportion of available pipeline slots, explaining the low IPC."

Both profiles show being frontend-bound in nearly 50%. This seems to be a common pattern. Zen 5 continues the existing trend - Zen 1 added uop cache, Zen 2 doubled the uop cache size, Zen 3 +50% wider dispatch, Zen 4 over 50+% of the uop cache, etc.

 

[inf64]

Both profiles show being frontend-bound in nearly 50%. This seems to be a common pattern. Zen 5 continues the existing trend - Zen 1 added uop cache, Zen 2 doubled the uop cache size, Zen 3 +50% wider dispatch, Zen 4 over 50+% of the uop cache, etc.

It's not just the mircoop cache that gets a boost in Zen 5 : AMD states they reworked the front end (re-pipelined the front end). It's a major redesign, but we have no details yet.

 

[PJVol]

I may have missed this, but were there any assumptions on whether Zen 6 will require a new socket?
Just curious of what actual AM5 lifespan is.

 

[DrMrLordX]

I may have missed this, but were there any assumptions on whether Zen 6 will require a new socket?
Just curious of what actual AM5 lifespan is.

Pretty sure they said 2026 back in June.

 

[rtxtwt]

AMD announces new mobile parts every January, so we should get mobile Zen 5 at minimum.

Intel is dropping Raptor Lake Refresh now and Arrow Lake H2 2024. If Zen 5 is a zinger, AMD will want to release it ASAP, that way they can have at least a year of market leadership.

I'm afraid there would be no Zen5 at January. Only teaser.

OTOH, few months ago Zen5 DT completion had been already planned to be Oct-Nov, mass production could happen at this timeframe, and there were about 4 months gap between completion to release since Zen2, so you can expect the actual release could happen in 1H2024 or even as early as Mar-Apr.

Mass production could even happening right now when I type this message.

 

[DisEnchantment]

Looks like there is +1 AGU as well besides what I summarized earlier. Will update once more data is available, or when product is launched otherwise.

 

[BorisTheBlade82]

Not sure if this has already been posted: https://chipsandcheese.com/2023/09/06/hot-chips-2023-characterizing-gaming-workloads-on-zen-4/

View attachment 86560

"Both gaming workloads are overwhelmingly frontend bound. They’re significantly backend bound as well, and lose further throughput from bad speculation. Useful work occupies a relatively minor proportion of available pipeline slots, explaining the low IPC."

Zen 5 main design goals:
View attachment 86562

Looks like Zen 5 will address the main bottlenecks in Zen 4, at least when gaming is concerned. Fun times for Arrow Lake

The thing is this: In each pipelined system, there are bottlenecks - be it a production line in a factory or a CPU. These bottlenecks might shift depending on the workload, which makes it important to define "common" workloads as optimization targets. And whenever you widen one bottleneck, another one will arise, that becomes the tightest part of the system.
So after having refined everything else except the Front End for several generations now, this is just the logical approach. Of course, nowadays, it is as important to keep high energy efficiency as to maximize throughput, which makes this a highly complex problem to solve.

 

[JoeRambo]

Looks like there is +1 AGU as well besides what I summarized earlier.

How else they would handle 4 loads per clock? That's pretty much implied.
The real question is about load width. Some people took "512bit FPU" and ran away with 4x512bit loads per cycle. That would be completely stupid and "non-AMD" thing to do.
I expect them to have 4x256bit loads and 2x256bit stores per cycle that can be changed to 2x512 / 1x512 and that is already more than plenty.

 

[HurleyBird]

Increased IPC increases power consumption.

I don't think that's coherent. An architectural change that increases IPC may or may not increase power consumption, but when you go over your power budget, with few exceptions, you reduce frequency. And IPC is always measured frequency normalized, typically at a frequency low enough and a power budget high enough to avoid throttling, which makes the idea of "IPC throttling" even less coherent.

If there is some sort of "IPC throttling" in Epyc it's pretty novel.

You guys are laying into @adroc_thurston like crazy to the point you go on the attack for nothing. I am just as critical of someone with no credibility showing up and making grandiose claims as the next person, but this IS a discussion and speculation thread, and the results WILL bear themselves out eventually. If he is right, he will be right, if he is wrong, he will be wrong.

At this point I'm pretty sure he has some inside info, but talks as if he knows absolutely everything, which isn't really how it works outside of a very select handful of people. Certainly wouldn't be the first person guilty of mixing info and speculation if that's the case.

More than that, he can be kind of annoying to interact with. He actually had a good point about the 2S Cinebench runs (still not sure about the order of scheduling inside the socket, whatever), but my God did it take a whole bunch of useless posts and repetitions to get to that point. When I asked for corroboration of Epyc "IPC throttling" he referenced some slide somewhere without providing a link or much information that would let one find this slide, but after last time, I didn't feel like going back and forth a dozen times before getting to an actual point (if there is one).