Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[rtxtwt]

Well the slide did mention 4 loads/ 2 stores per cycle, which would imply 4x 256 bit (AVX2) or 2x512bit (AVX512). If the core can sustain it, that would mean it doubles the FP throughput versus Genoa.

You know it well.

https://twitter.com/x/status/1689093514846724096

 

[eek2121]

Just because @adroc_thurston mentioned $999, doesn't mean he is right.
I don't think price is set at this point.

MSRP:
5950X -> $799
7950X(3D) -> $699
7950X saw a 32% increase in performance(TPU) compared to the predecessor, yet It cost less money. It saw a 51% increase in perf/$.
Of course this reduced price was likely also due to high platform cost vs Intel platform.
15% increase at $999 price point for Zen5 would mean 19% reduction in perf/$, so It's a nonsense.

I won't guess Zen5 performance, because I don't know.
What I know is that they have to set the price to be competitive in perf/$ not just against Intel but also Zen4.

I wanted to post this yesterday in response to some other posters, but I have been busy.

Note that due to the fact that the CCDs were slightly larger for Zen 3 vs. Zen 2, MSRP was increased ($50 increase for the 3950x -> 5950X from $749 to $799)

Zen 4 CCDs were smaller (though the silicon costed more), so the launch price actually gave them higher margins vs. Zen 3. The price drop likely led to normalization of margins, though I imagine some of that was eaten by distributors and/or retailers.

As I alluded to before, AMD is going to want to maintain their margins, so any increase in relative size will include a corresponding price increase.

Zen 5 will be more expensive, and yes, final pricing has not been decided.

I think a lot of people misconstrued my words (or perhaps I did a poor job of writing) into saying Zen 5 would not be bigger. I wasn’t implying that at all. I was merely trying to state that AMD won’t be subsidizing any increase in die size. If Zen 5 die sizes are larger (which is likely), pricing WILL go up.

I don’t think @adroc_thurston was claiming to know the pricing in advance, but does know what most of us know: Zen 5 is a bigger core, and still uses largely the same process as Zen 4, so the price has to increase.

You absolutely should not expect a $749-$799 MSRP for a halo SKU.

My guess would be $849-$899 depending on where Zen 5 lands competitively.

I also do not expect Zen 5 and Arrow Lake to be significantly far apart in terms of performance. Arrow Lake is 5+% faster than the upcoming Intel chips, and the upcoming Intel chips are already ahead of non-x3D parts in terms of general performance, and even beat the x3D parts for some gaming benchmarks. Add another 5-15% on top of that and Zen 5 is going to have a very tall hill to climb just to reach parity, much less gain leadership.

I absolutely expect Zen 5 to edge out the competition, however. I also expect Intel to still win certain workloads.

Due to this, competition will be a factor in determining pricing, and if you aren’t in a hurry to upgrade , I would definitely wait until Arrow lake drops as Zen 5 prices will have come down by then. Of course, for many of us, Zen 5 will still be a Day 1 purchase. 🤣

 

[maddie]

For me as a non-native english speaker, it's not quite clear how one should interpret "going to" at 1:06:10, in
"the rdna 3 is going to deliver another greater than 50% perf/w uplift over the previous gen"
Can someone clarify?

RDNA3 was not yet released, so those were expected values. He was telling the audience what would ( "going to" ) be the situation when the product was released. Wrong of course, in the end.

Hope it helps.

 

[jpiniero]

Zen 4 CCDs were smaller (though the silicon costed more), so the launch price actually gave them higher margins vs. Zen 3. The price drop likely led to normalization of margins, though I imagine some of that was eaten by distributors and/or retailers.

Don't forget that the IO die went from cheap GloFo to expensive N6. There's a reason that AMD's client business is unprofitable now, AMD won't/can't get the higher ASPs to compensate for the higher costs.

It wouldn't be a surprise to see them try again.

 

[JoeRambo]

Well the slide did mention 4 loads/ 2 stores per cycle, which would imply 4x 256 bit (AVX2) or 2x512bit (AVX512). If the core can sustain it, that would mean it doubles the FP throughput versus Genoa.

Currently Z3/Z4 has 3 loads of 64bits, but just 2 loads of 256bits in vector side. Having 4 load or 2x512 capability does not automatically result in 4x256 bits on vector side.

And the "sustain" part is very questionable too. Are they blowing up register file with all these ports required, on top of very likely increase in "raw" number of PRF registers to serve the rest of enlarged OoO machine.

2x512 is safe* bet, 3x256 is very safe* too, can they do 4x256 which is by far the most interesting to desktop/gaming => remains to be seen. So a question of "matching" GLC vs "beating" it.

What could happen to Z5 -> after being originally planned on N3 gen process, they had to retarget it on N5 and in the process they needed to cut down some structures. If this theory is correct, Z6 would contain quite some of this "latent" IPC gain.

* safe to bet with AMD's slide of 512 FPU, but will that happen on all SKUs?

 

[igor_kavinski]

That said, I'd rather Adroc stay on the forum than leave. Even if there's a lot of noise, anything with some signal can be valuable.

I don't know. I think someone could be playing games with us. He responds like a rumor-trained ChatGPT. Of all the posters here, even the ones who have some communication impediment due to English being a foreign language to them, adroc just sounds weird. Curt responses like someone is paying him to respond to as many posters as possible in the least amount of time, without going into much detail.

 

[Ajay]

sure it does ????

Well, looking at it again its just poorly worded.

 

[Glo.]

Its funny that we are at the stage of discussion that we are more interested in discussing about person, rather than what they say about Zen 5.

 

[dr1337]

Its funny that we are at the stage of discussion that we are more interested in discussing about person, rather than what they say about Zen 5.

I am not interested in either drama or talking about MLID rumors as if they're gospel. What people are saying is important and so is the true source of the things they're saying.

I hope so, always wanted to be a manifestation of someone's schizophrenia.

If some people are only here to sow drama then that's probably why other people are talking about them.


AMD is famous for its hype train, I guess this is the new incarnation since they've become leak tight.

 

[inf64]

Currently Z3/Z4 has 3 loads of 64bits, but just 2 loads of 256bits in vector side. Having 4 load or 2x512 capability does not automatically result in 4x256 bits on vector side.

And the "sustain" part is very questionable too. Are they blowing up register file with all these ports required, on top of very likely increase in "raw" number of PRF registers to serve the rest of enlarged OoO machine.

2x512 is safe* bet, 3x256 is very safe* too, can they do 4x256 which is by far the most interesting to desktop/gaming => remains to be seen. So a question of "matching" GLC vs "beating" it.

What could happen to Z5 -> after being originally planned on N3 gen process, they had to retarget it on N5 and in the process they needed to cut down some structures. If this theory is correct, Z6 would contain quite some of this "latent" IPC gain.

* safe to bet with AMD's slide of 512 FPU, but will that happen on all SKUs?

Well, AMD increased the AGU count to 4 so I think it's very much possible to have 4x256bit loads per cycle, but whether this can be utilized by the FP unit in the AVX2 code is a big question mark. They list 3 FP subunits in the slide, which looks similar to Zen3/4 allocation. As for matching Golden Cove, AMD already has same or better AVX (even with AVX512) throughput per core, so Zen 5 can only take it to another level vs the competition.

 

[igor_kavinski]

As for marching Golden Cove, AMD already has same or better AVX (even with AVX512) throughput per core, so Zen 5 can only take it to another level vs the competition.

Driving the nail a little bit harder into Intel's coffin

I hope they are careful and don't use too large a hammer. We don't want Intel's coffin to get cracked

 

[yuri69]

Zen 2@72mm2 --> Zen 3@80.7mm2 --> Zen 4@66mm2

Let's say a minor bump of 12% CCD size, Zen 4@66mm2 --> Zen 5@74mm2
That is a 35% increase in core area (with L2/L1 remaining largely same) 600+ MTr per core

A 20% bump in CCD size, i.e. 80mm2 Zen 5 CCD would lead to 60% bigger core.

I recall very similar calculations involving die size and MTr per-core making the Zen 4 a clear IPC monster.

 

[DisEnchantment]

I recall very similar calculations involving die size and MTr per-core making the Zen 4 a clear IPC monster.

Zen 4 is the the generation with the highest gains in the Zen era so however they spent the transistor budget must have been a job well done.
Cranking up clocks also need transistors.
I have strong doubts Zen 4's 28% ST perf gain is reachable by the supposedly fat Zen 5 core.

 

[JoeRambo]

Well, AMD increased the AGU count to 4 so I think it's very much possible to have 4x256bit loads per cycle,

They have 3 AGU's now, but only 2x256 bits per cycle, and on Intel we have 2x512, but 3x256 ( can be said to be limited by "AGU's", but in reality cache / PRF port limitations apply as well ).

 

[Thibsie]

For me the most exciting thing with Zen5 isn't really the upcoming Perfs gains but that it is a mostly all rebuilt core. Which means there should be relatively low hanging fruits to get for Zen6/Zen7.

I'm very curious. I won't be able to upgrade. My 5600X is fine and these days I don't even have to time to play with my 6800XT .

I'm more urgent need of a 'not to old Mac mini ' although hackintosh is a way too (running specific app only available for iOS, MacOS etc.). I hate that but what can I do? Sad.

 

[igor_kavinski]

I'm more urgent need of a 'not to old Mac mini ' although hackintosh is a way too (running specific app only available for iOS, MacOS etc.). I hate that but what can I do? Sad.

If that app isn't very CPU intensive and not a multimedia app, it should run fine in a VMware VM of MacOS. It's easy to find pre-built VMDKs for those if you look around.

 

[Joe NYC]

I just want Strix Halo in a compact form factor, like a mini PC or laptop, and would be happy to pay a premium for it provided it offers top notch ST performance and a solid iGPU that can drive 1440p60 with ease.

In theory, Strix Halo could also have a V-Cache, which would make it a really nice CPU.

 

[Joe NYC]

I think AMD leaks like a sieve. I don’t think RDNA3 was kept a secret but just hyped beyond belief by the usual suspects to where it was always going to underperform relative to expectations.

I am trying to wrap my head around what you are saying here, but I can't.

It seems like you are saying AMD intentionally over promised and undelivered. Which is something that makes no sense in this universe.

Maybe in your universe, it does make sense.

 

[igor_kavinski]

AMD's GPU division is their limp dog they preferred they didn't have but don't put it down coz it's not totally useless and also coz AMD is not full of heartless illegitimately born humans. Yet.

 

[H433x0n]

I am trying to wrap my head around what you are saying here, but I can't.

It seems like you are saying AMD intentionally over promised and undelivered. Which is something that makes no sense in this universe.

Maybe in your universe, it does make sense.

You're reading way too much into this.

I don't think these leaks are purposely done by AMD (or Intel for that matter). It's an inevitable consequence of having tens of thousands of employees. I'd imagine that AMD would want to restrict these leaks since it sets them up in an unwinnable position where hype and expectations are set so high that they're totally unreachable.

 

[adroc_thurston]

AMD's GPU division is their limp dog they preferred they didn't have but don't put it down coz it's not totally useless and also coz AMD is not full of heartless illegitimately born humans. Yet.

Nope.
Major money is being thrown there explicitly.

 

[Hitman928]

Nope.
Major money is being thrown there explicitly.

Good thing they continued to invest as the AI boom (LLM in particular) could potentially be their most profitable market ever, at least for as long as that market can sustain itself.

 

[igor_kavinski]

Major money is being thrown there explicitly.

Into AI stuff. Not for us peasants.

It's ironic that the only one that really wants to appease us peasant gamers right now is Intel.

 

[TESKATLIPOKA]

In theory, Strix Halo could also have a V-Cache, which would make it a really nice CPU.

Strix Halo will be the most costly APU they have for the client segment, thanks to IOD.
I don't think they will throw extra cache on top of that, when It's aimed for mobile, which doesn't have high margins.

 

[Glo.]

Strix Halo will be the most costly APU they have for the client segment, thanks to IOD.
I don't think they will throw extra cache on top of that, when It's aimed for mobile, which doesn't have high margins.

Expect that next gen APUs from AMD will be partitioned with IO dies.

Even the ones that would be replacing Strix Point, standard(not saying that replacement for Strix Point will be chiplet based). Its just a matter of time and... costs.