Don't hate me for this, but right now I wonder if Strix' iGPU will be any faster than Phoenix. If Strix really doesn't have a bigger GPU Cache (which is likely, because Microsoft wants big AIE) I think it will be completely memory bound.I'll preface this by saying I don't know Strix Point perf numbers, but I still wouldn't expect a 50% bump over PHX personally.
I'm expecting more along the lines of ~25-30% perf at best. Memory bandwidth is the concern really, PHX seems massively mem bw bound by 28w.
Strix Point vs PhoenixDon't hate me for this, but right now I wonder if Strix' iGPU will be any faster than Phoenix. If Strix really doesn't have a bigger GPU Cache (which is likely, because Microsoft wants big AIE) I think it will be completely memory bound.
I mean look at Phoenix:
7600 is ~8-10% faster than 6650XT at mostly same clocks in most reviews, so that's what RDNA3 delivers over RDNA2. 780M clocks 18% (2.8GHz vs 2.4GHz) higher than 680M. So expected performance uplift of 780M would be in the 25-30% region. However, with same RAM it's barely 10% faster, more like 5%. If Strix just dumps 2 more WGPs in there i don't see how it is any faster than 780M at ISO RAM.
That's what it supports, but OEM decides what's in there at the end.LPDDR5X-8533 vs LPDDR5X-7500
ZEN5 is a lot wider than ZEN4, there's a reason it uses 4+8 Design that probably takes the same space as a 8 ZEN5 Design. 50% more L2, 50% more L3, 2 more WGPs that may also be bigger because of RDNA3.5. Probably more/more modern IO (PCIe 5.0?). Bigger AIE. That's a lot to fit in those 47mm^2, don't you think? It's N4 vs N4(P?) after all.There's minor uplift in RAM bandwidth. Also they are adding 47 mm² of Silicon. Surely, that's enough to squeeze in a bigger GPU cache?
Defining real-world benches might be helpful for this discussion?
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TweakTown also measured a +9% IPC advantage for Raptor Lake versus Zen4:
Tweakers.net found about the same:
View attachment 91441
Overclockers tested a few more:
STX
TSMC N4P 225mm²
4c Zen 5 L3: 16 MB L2: 4 MB
8c Zen 5C L3: 16 MB L2: 8 MB
8 WGP RDNA3+
64 AIE tile
DDR5-5600 / LPDDR5X-8533
28-35+ W
Got corrected immediately to 8MB L3 for the ZEN5c CCX. So the 4 ZEN5 Cores get 16MB L3, the 8 ZEN5c Cores get 8MB L3.
Describing two separate caches by the sum of their sizes is alright when you discuss just area, but functionally that's a rather idealized quantification and overstates the usefulness of these caches in many relevant scenarios. Personally I would expect the designers of a mobile CPU to go for a unified last level cache. But who knows, CPUs with stranger properties have been released before.Hmm, if that is correction, then total L3 cache of STX is 24MB....50% larger than PHX
And will this be enough? 6800m which has the same 40CU gets up to 384GB/s as per AMD.256 bit + LPDDR5X 8533.
= 273 GB/s
And will this be enough? 6800m which has the same 40CU gets up to 384GB/s as per AMD.
That's why my question in the first place. A chip like this without being properly fed it's a bit of a waste. Unless I miss something.
I don't know, there's no new informations about production recently. But some gossip suggest Zen5 would utilize XDNA2 architecture.Why smallish amount? Some production related hiccups?
How high can they go? CPU wise, 40-65W is about enough... For GPU, sky's the limit. I wish they would do 100W at least, but I admit I have no idea if it is a mobile only or mixed desktop mobile partClocks may not be that high on Strix Halo. Depends on how high the power draw is going to go.
We receive Zen6 DT codename before Zen5 release
I don't know, there's no new informations about production recently. But some gossip suggest Zen5 would utilize XDNA2 architecture.
My first message here ... hi everybody !!!
I've been reading you silently for several months ... and ... I admit it : I am an enthusiast ignorant ... BUT , I would like to know ...
My question is :
I would like to know whether AMD were able to 'roll-out' Strix Point at ... let's say May ... why would they do it on October instead ??
I can think of 'commercial reasons' ... to give some time Hawk Point to get sell ...
On the other hand ... from my lack of knowledge, I think the soonest Strix Point (Zen 5) hits retailers' shelves ... the more market share AMD will take away from Intel ... at least as far as the laptop market is concerned.
Please ... shed some 'light' ...
Regards.
Soo... how's AMD gonna feed so many hungry Strix Halo CPU, GPU and AI cores?
How high can they go? CPU wise, 40-65W is about enough... For GPU, sky's the limit. I wish they would do 100W at least, but I admit I have no idea if it is a mobile only or mixed desktop mobile part
L3 cache is not separate, I don't know why you think It's separate.Describing two separate caches by the sum of their sizes is alright when you discuss just area, but functionally that's a rather idealized quantification and overstates the usefulness of these caches in many relevant scenarios. Personally I would expect the designers of a mobile CPU to go for a unified last level cache. But who knows, CPUs with stranger properties have been released before.
@ikjadoon, why are you first asking @Markfw to define real-world benchmarks, then leave the real world and provide Cinebench 1T figures? The Cinebench benchmark measures performance of a rendering engine which, in the real world, is used for widely parallel problems and, importantly, in its much more effective GPGPU implementation, not in the plain CPU implementation anymore these days.
I understand that @Markfw was primarily referring to fully parallel scientific computing. E.g. molecular dynamics, telescope data processing, number-theoretical transforms... That's often n×1-copies×threads, sometimes n×m-copies×threads. I am running such stuff myself and occasionally implemented actual reproducible benchmarks based on selected workunits of such science tasks.
...
Anyway; this side discussion was started with a statement that Intel had "better IPC" (without further qualification) and the implication that this is one of the aspects why the poster thought that AMD should offer Zen 5 based products as soon as they can. Meanwhile we have seen that there are indeed situations in which higher clock-normalized performance is observed on Intel CPUs, while on the other hand everybody can have a different opinion on how much this fact can or should influence AMD's time-to-market efforts. :-)
Not to jump too much into this as I actually put more value in spec_int, but your real world application comparison actually favors Zen4. You have Cinebench r20 three times, Cinebench r23 once, then 2 other tests. So basically it shows that RPL leads Zen4 in Cinebench by about 10% but then Zen4 leads in 7Zip by about 10% and the "tie breaker" would be Wprime where Zen4 leads by about 20%. This leaves you with Zen4 being 6% faster per clock on average across the 3 different workloads. Even if you count CB R20 and R23 separately, Zen4 would still be about 2% faster on average in the shown tests.
If Strix doesn't change AMDs use of CCXs then it kinda is separate. The 4 ZEN5 Cores will have fast access to 16MB L3 and the 8 ZEN5c Cores will have fast access to 8MB L3. Cross CCX Latencies are usually much worse.L3 cache is not separate, I don't know why you think It's separate.
Aren't you comparing It to desktop CPUs, which have separate CCDs?If Strix doesn't change AMDs use of CCXs then it kinda is separate. The 4 ZEN5 Cores will have fast access to 16MB L3 and the 8 ZEN5c Cores will have fast access to 8MB L3. Cross CCX Latencies are usually much worse.
Everything I heard so far was 2 CCX, but idk. Renoir also had 2 CCX btw, each with only 4MB L3.Strix Point will have most likely a single CCX.
Only that twitter message, or how it was quoted here, made it look like that to me.L3 cache is not separate, I don't know why you think It's separate.
It's dual CCXes.Aren't you comparing It to desktop CPUs, which have separate CCDs?
Does PHX2's cache look to you like It's separate? But It's true, that It's only 6 cores in total.
Strix Point will have most likely a single CCX.
For sure? Can't say I am happy with this.It's dual CCXes.
PHX2 is single CCX, but STX is dual.
What's wrong with that setup?For sure? Can't say I am happy with this.
How would It look like?
4xZen5 -> CCX 1
8xZen5c -> CCX 2
Yep, that's what I suspected cause Allthewatt stated the L3 cache of Zen5 and Zen5c are seperated...so we are getting:-It's dual CCXes.
PHX2 is single CCX, but STX is dual.