Yeah I am assuming he’s using those internal APIs or something and the 11W figure is the full number someone else measured externally. M3 for example certainly consumes more than 4.76 watts in ST. Regardless yeah they blew up core power, albeit at least it’s way better than competitors still.Pretty significant increase in core power there between M3 and M4
In short: It's the very definition of resting on one's laurels.Why would they actually redesign the core though if the basics still work?
We thought that would happen with N3B/A16/M3. But it didn't.there is a major redesign coming soon for one of the following gens.
In the worst case Apple is actively looking for competent staff but so far "only" found ones capable of making the most of existing core designs. Redesigning cores to not only perform at the same level as the previous ones but significantly above that with added room for further improvements is kind of hard after you let leave all the staff previously involved in such evolution.We thought that would happen with N3B/A16/M3. But it didn't.
But then we thought it will happen with N3E/A18/M4. But that also hasn't happened.
So when?
According to mobile chip expert on Weibo, M3 was supposed to the core redesign but Apple wasn’t happy the performance uplift ie the IPC improvement. So they scraped it.We thought that would happen with N3B/A16/M3. But it didn't.
But then we thought it will happen with N3E/A18/M4. But that also hasn't happened.
So when?
You have no idea what I meant. My point is that Apple isn’t going to change their design philosophies which are targeted towards low power cores and running wide, and they’ve been doing this for *years* now, since inception.In short: It's the very definition of resting on one's laurels.
It's exploiting existing capabilities but doesn't prepare for future bigger improvements. Making the most of what's already there makes it seem like the product keeps up well in the competitive environment, but bigger jumps are essentially delayed up to the point where work on redesigns resume (and those actually turn out to be successful, which is never a given). Intel did it will all the Skylake derivatives and lost its IPC lead over that. Apple seems to be on the way to do the same right now unless there is a major redesign coming soon for one of the following gens.
Maybe you should write what you meant then? I'm just reading what you wrote, and you wrote "Why would they actually redesign the core". Redesigning the core every couple of generations is a prerequisite to always increase the room available for improvements, essentially rebalancing bottlenecks. This has nothing to do with changing some design philosophies or some such.You have no idea what I meant. My point is that Apple isn’t going to change their design philosophies which are targeted towards low power cores and running wide, and they’ve been doing this for *years* now, since inception.
I mean, “redesigning the core” is not at all something clear in these corners. People literally believe in “clean sheet designs” which is a very loose term these daysMaybe you should write what you meant then? I'm just reading what you wrote, and you wrote "Why would they actually redesign the core". Redesigning the core every couple of generations is a prerequisite to always increase the room available for improvements, essentially rebalancing bottlenecks. This has nothing to do with changing some design philosophies or some such.
Reading your further response it seems we actually agree, so I'll stop there.
Edit: And going by Geekerwan's microarchitecture analysis discussed in the other thread M4 may well constitute a redesigned core. Let's see.
That's really unfortunate as that's a rather basic step in evolutionary (not revolutionary, that'd be "clean sheet") development of silicon. To have technical discussions everybody should (try to) be on the same page. Recent discussions about odd and even Zen gens showed that some people don't seem to grasp the difference between designing schematic diagrams and allocating resources to units and connections on it.I mean, “redesigning the core” is not at all something clear in these corners.
It doesn't look like Apple has the know-how anymore to redesign the core. Every generation after M1 has been using the transistor budget to just widen existing structures. Like Jim Keller said, every so often you have to re-write the core and rebalance the structures. Even if the underlying building blocks are the same, how you use them to construct the core matters a lot more. AMD did it with Zen 3 and now they will redo it with Zen 5. It doesn't appear Apple did it at all within the last 3 years.
But having an as wide as possible machine isn't the way, the only way some may say, to achieve this great performance at lower clocks and power? Would be possible to achieve the same performance with a narrower core?
Intel LPE cores are hyper efficient. Can apple match that?Intel/AMD low-power core designs have no hope of beating this.
Did you not hear what I said?Intel LPE cores are hyper efficient. Can apple match that?
Likely. There are lots of tricks that boost your general core perf without going wider.
Just a question of what tradeoffs you're willing to make for your target workloads.
- Deeper structures - schedulers, ROB, PRF size
- Larger or faster caches (like Z, which has usually not been on the cutting edge of width but has generally had very large L1/L2)
- Non-committing runahead (like Power6) and its advanced cousin, speculative multithreading (like Rock)
- Branch predictor improvements
- Prefetch improvements
- Reduced op latencies
- For multithreaded performance - SMT, unusual shared cache configurations (like later SPARC gens), unusual shared core-resource configurations (like Bulldozer family or Freescale e6500)
Possible, it yes.
Is there any team able to build this unicorn of narrower machine that matches Apple?
But having an as wide as possible machine isn't the way, the only way some may say, to achieve this great performance at lower clocks and power? Would be possible to achieve the same performance with a narrower core?
In short: It's the very definition of resting on one's laurels.
It's exploiting existing capabilities but doesn't prepare for future bigger improvements. Making the most of what's already there makes it seem like the product keeps up well in the competitive environment, but bigger jumps are essentially delayed up to the point where work on redesigns resume (and those actually turn out to be successful, which is never a given). Intel did it will all the Skylake derivatives and lost its IPC lead over that. Apple seems to be on the way to do the same right now unless there is a major redesign coming soon for one of the following gens.
No. It's either to execute as many as possible instructions simultaneously or clock higher.
This isn't true at all.
One of the largest performance limiters in modern microarchitecture is correct branch prediction, which isn't about executing more ops at all, but rather about running ops as early as possible and wasting as little work as possible.
Cortex-X4 is wider than M3, and slower.
Wider as cpu ability to extract IPC from code. Technical details to achieve that are irrelevant, stating that Cortex-X4 is "wider" than M3 is massively oversimplification. Minor performance increase can be found by widening any state of cpu pipeline but as increasing area of execution will also increase power logarithmically good cpu designer should instead minimize every stage at their design to find optimal performance/power and extract max clocks. Which clearly Apple does better than any of their rival today. Which actually is very curious case, they don't need to be fastest, they really don't chase maximum performance from their silicon and still they got the fastest cpu design. They sure make their rivals look incompetent.