Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[eek2121]

Also just want to add it would be funny if his IPC estimates for GNR is accurate because it uses LNC lol

You mean guesses? Guess often enough and eventually you'll get something right.

 

[SiliconFly]

Note: the portion in red is NOT what MLID said. So the rest of your math is not what he claims either.

He specifically claimed (without any evidence) of 30% to 40% ST faster than Raptor Lake not Meteor Lake (and not even Raptor Lake Refresh). That would be 30% to 40% ST with 2 node shrinks and a new core (3 node shrinks if you count skipping Intel 3). That would require Arrow Lake turbo to be roughly, mid 6 GHz to mid 7 GHz depending on IPC gains.

I'm not saying MLID is correct, but you took his rumors way past even what MLID claims.

A very interesting tweet from Raichu regarding MLID leaks:

https://twitter.com/x/status/1664585493953249283

(Rumor chain: MLID->wccftech->Hassan Mujtaba->Raichu)

In short, raichu simply says, it's fake.

 

[eek2121]

The only sense I could even plausibly see MTL being more efficient than an M2 Mac is the same one in which Rembrandt is close or more efficient at 15-25W workloads where the M2 is at full tilt (measured from the wall, full package power) on a purely MT workload. With 4+4 and 4 of those littles only adding so much, if you measure at an arbitrary power point, you could absolutely find e.g. a MTL 2+8 or 6+8 unit more efficient at some high point on Apple's efficiency curve, in a purely multithreaded workload, even if the cores won't stand a chance on ST perf/w anywhere.

Otherwise though there's really no way. And in practice real workloads on a PC, mobile specifically, aren't invariably logging on to churn at 25W for two hours before plugging the system in. I mean, efficiency there is important still, but for me compilation/builds themselves aren't the majority of my time. Instead relatively snappy ST without gunning it to 15-20W & efficiency cores that can take care of background tasks at reasonable speeds & a fraction of the energy consumption a P core uses are invaluable, not to mention low idle draw.

Anyways, looking at where ADL is, optimistically shutting off the compute tile will be big for idle power, and more cache + Intel 4 could really take MTL closer to Zen 4 than currently. But I'm skeptical they're going to have an answer for Apple, even -40% on power iso-perf probably won't take Redwood Cove to Avalanche's league below 5-6 watts, nor put Intel's E Cores at Apple's class or even A7x class on energy consumption. Even AMD isn't there yet on the former.

The win for Intel would be putting MTL idle draw much closer to Ice/Tiger Lake, which seems feasible, and then some general power improvements under load from the process at moderate voltages. With that, I could see Intel back on the map as "acceptable" to good vs Zen 4. They'd have idle back to acceptable if not good ranges unlike ADL, but they'd have MT unlike with TGL and ICL SKUs (along with some ST improvements), some power improvement too, and notably I think ADL's iGPU is supposed to be pretty competitive.

I've actually seen some comparisons between the 7950x, the 13900k, and the M2 Ultra. One of the issues I have with these comparisons is that the M2 is a laptop chip. If the comparisons had, say, a Ryzen 7945HX, I would agree with you, however, comparing Zen 4 or Raptor Lake S to an Apple mobile processor is an Apples to Oranges comparison.

Show me the lower power chips and where they stand.

Here is Ars Technica's chart on low vs. high power chips:

Even that one is suspect because with my own handbrake benchmarks, the 7950X at lower TDPs was MUCH more competitive than in this chart.

Also, the M2 Ultra is uncompetitive in terms of absolute performance. It only wins at perf/watt, so it is clearly a mobile oriented chip.

 

[adroc_thurston]

lets look at great ARM SoCs like Apple's and Qualcomms

Again, it's just a question of validation.

Arrow uses the same core design???

If only your average SoC was just sea-of-cores.

 

[Exist50]

Arrow uses the same core design???

Too vague for me to tell how much he/she knows, but @adroc_thurston is certainly right that LNL is by far the more interesting of the two.

Lunar Lake isn’t planned to be on N3, not at the moment at least.

Lunar Lake is and always was on N3.

Ha, Golden Pig Upgrade @ Bilibili claimed that Intel 20A is gone missing....

As far as I'm aware, this is not true, though it's possible I'm behind the curve. I'd take that claim with quite a bit of salt, however.

 

[Khato]

Yeah, MTL performance will definitely be on par or greater than RPL while being more efficient.

It's plausible that notable clock speed regression is with respect to the e-cores rather than p-cores.

 

[mikk]

It'll hit 5GHz. But certainly MTL won't be noteworthy from a CPU perspective.

This was my expectation but what is the big deal about then? We know since ages that MTL will bring a sidegrade at best when it comes to 1T performance, nobody expects RPL boost clocks. I would expect at least ADL boost clocks though, means at least 5.0 Ghz (i9-12900H). adroc_thurston implies it's really bad like catastrophic. If it hits at least 5 Ghz it's not bad to me.

I expect much better PL1 clocks however because of Intel 4, efficiency is the key there. Otherwise it would be a disappointment...

He just repeats whatever he sees on Weibo, a classical Chinese tourist in every way possible.

I don't think so, sorry. You could prove me wrong but I doubt you can.

 

[Exist50]

120 and yea, there's more to server chips than just raw core counts.
AmpereOne is 192c, but lol. Lmao even.
AMD makes better cores than anyone else in the industry and you will learn it the hard way!

Well you've seen the GNR perf target from BHS-AP platform guide (it's 2x EMR which is lol/lmao), and Turin idk if I can say the numbers yet, but a lot faster than that even.

2x EMR would very soundly beat Genoa. And yes, there's more than core count, hence my comments about the Zen 5 hype train. Anyway, we shall see.

 

[Exist50]

I literally know the numbers lol.

Ok, then why not post them so we can reference later? It's not like you have an existing track record in this forum.

 

[Exist50]

It is, RWC's aren't that much faster per thread and power there is no good at all.
LNC is the interesting one and genuinely is a rather capable core but that's not what GNR has so...
Again, focus on client parts.
DCAI is totaled in both DC and, well, AI.

Yea I was kinda amazed when I saw Eldora A0 results.

Second, Zen3 was the first one.
Zen5 is by far a more ambitious one.
Mikey C. wasn't joking about daydreaming the thing.

Dude, I think you're working with incomplete information. That, or you're just feeding into the hype. Might want to tone it down a bit...

 

[Exist50]

No you haven't, then.
Turin socket perf targets are known for both 96c and 128c configs.

Then stick around this forum long enough for us to see. Because right now, all I'm seeing is unsupported hype.

 

[H433x0n]

Because a whole lot of them are just 1t benches (or generally don't scale out to 192c at all), which Turin will absolutely smoke anyway, kinda the idea, even.
Those high-CC chips aren't really made for that.
I mean, STH had to spin an additional kernel comp instance for their usual Linux kernel compilation bench specifically because of that.

That’s sort of cherry picking, which is exactly my point. You can’t point to a 30-50% advantage unless you begin hand selecting certain benchmarks that favor your point. Rendering also isn’t a top concern for the clients purchasing these products.

Genoa customer traction is very real.

My interests aren’t data center, I care more about process technology and client products.

 

[Glo.]

Really? Tell me one existing Ryzen mobile chip that has a GPU that's even half as good as MTL's.

Both 680M and 780M Radeon iGPUs are much faster than 50% of MTLs supposed performance.

780M, for example scores 2800 pts in 3D Mark Time Spy Graphics. MTL-P 128 EU iGPU is supposed to score here around 3500 pts. 680 in TS Graphics got 2400 pts, average.

You are vastly underestimating the performance of iGPUs these days.

 

[Geddagod]

x86 SunnyCove failed? What? SunnyCove is a redesigned and expanded core that has 38% more transistors than SkyLake. Despite still having 4-way decoding and 4 ALUs, it has an average of 18% higher IPC. Zen 3 with 19% IPC increase is a huge profit, and SunnyCove with 18% higher IPC is already a failed architecture? Really?

Lil bro I said it "wasn't all that good". And where did you get that transistor count number?
And ye SNC wasn't that good lol. Mid core. SNC didn't improve perf/watt vs CML mobile, had a ST freq regression, and increased area by like 25%. Zen 3 increased perf/watt by like 15-20%, increased ST freq, increased freq/power across the curve , and increased area by 10-15%. So ye, Zen 3 is a "huge profit" and SNC is pretty bad tbh.
And before we blame 10nm for SNC too much, we should remember than Cypress Cove fixed the ST freq regression, but still consumed more power iso frequency vs comet lake, and by a good chunk iirc. Zen 3 is incredibly impressive with the fact that it didn't. And oh ye, CYPC is a whopping 33% larger per core vs SKL.

Actually, Sunny Cove was a good product, but had yield issues (on the original 10nm node). And it got overshadowed by Comet Lake (14nm++++).

SNC shouldn't be considered a good product if it got overshadowed by a product on the previous node.

 

[FangBLade]

Cope harder , process is going to have ~0 IPC effect.
moving to TSMC would limit the one advantage intel has when it comes to raw total single thread performance.... clock rate........

He's just trolling you; he knows very well that what he's writing has no connection to the truth. He does this on other forums as well; some have even banned him for it .

You were just warned on Tuesday for calling people trolls. You are filling in spaces on your ban hammer bingo card. FYI: you are not allowed to edit post containing moderator comments. - CPU mod DAPUNISHER

 

[Glo.]

And let AMD eat more of their lunch? That's a laughable thought.

Mobile is where the battle will be the biggest and toughest between AMD and Intel in upcoming years.

 

[JoeRambo]

Why do you say that? Do you have any recent leaks?
I thought ARL was supposed to be the first itineration of the new core design?

Are leaks really needed? Does anyone here believes that Intel will take Redwood Cove ( in Meteor Lake, pretty much a known perf quantity at this point due to leaks ) and completely turn it around for one generation in Arrow Lake on same socket for massive performance increase. And then throw it away to introduce Lion Cove in Generation 16?
Not really, right?
Intel already has people committing stuff for Lion Cove in perfmon, but somehow this 30% IPC increase magic mushroom architecture is skipped, even if those advances would require ton of PMU updates in 2024 for all these new ports and capabilities.
Yeah right.

I don't have any info, but common sense says -> Arrow Lake is using same Redwood Cove on new process, likely increasing L2 to 3MB and maybe L3 to some more per core. That's it. And clocking better than 5Ghz incarnation in Meteor Lake.

https://twitter.com/x/status/1689646409329569792

That's right, Your 30% IPC core does not even have it's own CPUID branch for PMU "selection". Guess what current Intel's core does not have one as well? Hint, the one that increased L2 to 2MB and has 100% identical PMU.

 

[Hulk]

Could GoldenCove be so close to perfectly exploiting the limits of 6-way x86 decoding?Even Zen 3 and Zen 4 with 4-way x86 decoding have largely comparable capabilities to GoldenCove.According to rumors, Zen 5 will also gain x86 6-way decoding.Isn't it possible that RedwoodCove, with the already known improvements, can gain even about 15% higher IPC?

Intel has a history (since Conroe) of improving either the front end or back end and then on the next architecture opening up the other end.

WARNING! Wild speculation ahead...

While there is obviously more to architecture than decoders and execution ports they are a good indication of what Intel is thinking as to balancing core throughput. Increases/improvements in other structures must also occur to kept the front/back end "fed."

Haswell/Broad well increased execution ports from 6 to 8.
Skylake added a decoder from 4 to 5, thus opening up the front end.
Sunny/Willow Cove added two more execution ports increasing the total to 10.
Golden Cove opened up both end adding two exe ports making the total 12 and adding another decoder bring that total to 6.

The fact that Intel increased the number of both execution ports and decoders in one architecture could mean that they feel as though the architecture is balanced, meaning meaningful gains will only come from making the core significantly wider or making some as yet unknown enhancements.

Or the core is plenty wide but currently held back by other structures such as buffers, registers, prefetch logic, micro-op cache, cache sizes, etc... or a combination thus fully utilizing the current Golden Cove front/back end.

 

[FangBLade]

Shouldn't you have replied to @SiliconFly instead?

I put him on ignore, we won't revisit that topic and go off-topic again.

 

[H433x0n]

14900K is just a rebranded 13900KS, it won't change anything in the performance stack.

It's a rebranded 13900K with process node tweaks to allow +200mhz clocks at iso power. It's a refresh so I don't think people are expecting much.

It will change the performance stack, just not for that long. Across the board 14600K, 14700K and 14900K will get a ~5% ST performance bump. This puts the 14900K ST performance ~15% higher than 7950X. That's not a negligible difference.

 

[inf64]

Less than 9 hours for MTL announcement! God knows what they're gonna reveal!

If it turns out to be a t, Intel may never ever recover from that shock.

Disappointment how exactly? What are you expecting MTL to do and why would it spell doom and gloom for intel?

 

[H433x0n]

I'm sorry to spoil your party but Zen5 is very much a fat IPC bump with a few bins of speed loss.
It is what it is; the thing's sampled far and wide even in the Strix form by now.

I consider 20% IPC gain a fat bump. They’d need a ~25% IPC increase to break even with a 300mhz clock regression, a ~22-23% IPC increase to break even with a 200mhz clock regression.

Literally every single numbered AMD bump was at least 30% 1t. lol.

Not sure what you meant by this but I’m assuming you meant previous generations. They’ve only gotten a 30% 1T improvement in a single generation once with Zen 4 and it came with a 700mhz higher clocks, a new node and DDR5. Zen 5 isn’t working with the same conditions that gave Zen 4 that big boost. It’s got to all be done with raw IPC.

 

[JoeRambo]

Edit: Why exactly is it more valid to test at JEDEC memory speeds again? Who’s buying a 7950X and 13900K and running JEDEC DDR5-4800?

It is only valid if JEDEC memory speeds are combined with JEDEC memory latency and sane, JEDEC defaults for other timings. Anandtech used to do this, and it was great even for enthusiast like me to provide baseline performance without memory tuning.

Other reviewers use various intellectually dishonest settings like:

1) "We test JEDEC speeds" and proceed to test at 5200CL32 for one vendor and 5600CL38 for other, subtle, but gives more advantage at 5200'ish speeds.
2) "We test at carbon copy timings and settings for both vendors" and proceed to test @ 6000CL32 when in fact it is edge of what is possible on vendor A at early maturity of platform and vendor B would happily run some 7400+ speeds with same effort involved.
3) Outright strange results for one vendor or another, where the rest of the web doesn't agree with them or their 'ordering' within vendor or between them. These "results" are great boon to certain faction warriors here.

For (3) it could be simply motherboards training, BIOS pecularities etc. Or sometimes even unscrupulous messing with secondary and tertiary timings. There are ways to boost and lower performance in trivial and more sophisticated ways, i think i'd easily manage to make FPS in some more sensitive game change +-10% with just tRFC and tREFI set "properly".

 

[Hitman928]

Actually, chiplets is an umbrella term used to denote many type of packaging. For example. Infinity Fabric based MCM (AMD), Interposer based Foveros (Intel), older EMIB bridges (Intel) are all now known as chiplets.

Just for info, another interesting thing is, contrary to popular belief, Intel came out with chiplet-based CPU i7-8000 series CPUs 1.5 years before AMD. It was a Kaby Lake CPU tile & a Vega GPU tile on substrate linked by a EMIB bridge. But it was never mainstream. Two years later Intel came out with another chiplet-based CPU Lakefield, but that too wasn't mainstream. MTL is.

(See: link, types, AT 8809, Intel Ark, zen 2 release)

Yes, there are multiple ways of producing a chiplet solution through various packaging technologies. They all have things in common though that the original C2Q didn't. I would also argue that Kaby Lake -G really wasn't a chiplet solution (though I could see an argument that it was) but Lakefield certainly was.

 

[inf64]

RWC IPC about the same and Crestmont 4-6% better IPC in average, this is what Intel said. Redwood Cove in Granite Rapids seems different.

Anyone remembers this MLID "leak"?

Intel 14th Gen Core 'Meteor Lake': 15-21% IPC boost over Raptor Lake

Intel's new 14th Gen Core 'Meteor Lake' CPUs rumored to have 15-21% more IPC performance over 13th Gen Core 'Raptor Lake' CPUs.

www.tweaktown.com

"
We are being teased with 15-21% increases in IPC performance with the new Redwood Cove architecture over the Raptor Cove architecture, but with MLID apologizing for the huge range (15-21%) but I think that's fine."

No biggie, MLID missed it will be 0-1% , just a 100% failed prediction. I posted this here just to show how this guy either :
1) has no real sources
2) is making it all up for clicks and
3) has multiple "sources" who are actually trolls and who feed him BS info all the time