Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[JoeRambo]

And as seen, both regular and C-cores share shame ring and L3-cache.

I assume you mean "same", as there is nothing shameful to share L3


AMD is following Intel's footsteps in hybrid CPUs, but with different flavor to save area:

1) Intel chose to have cores clustered and sharing L2, providing maximum area savings at the cost of designing completely different core with different performance characteristics and without AVX512
2) AMD went for same core, same instruction set, area saving due to targeting lower clocks. Looking at that floorplan, if their goal was to was save area, results don't seem that spectacular. 4 full P cores would fit and depending on clocks targets would provide benefits of homogeneous SoC at unknown at this point MT performance penalty.
Heck, 6P would not break bank either on this floorplan.

 

[naukkis]

I assume you mean "same", as there is nothing shameful to share L3

Yeah, just typo. Some did speculate it to be two CCX-design.

2) AMD went for same core, same instruction set, area saving due to targeting lower clocks. Looking at that floorplan, if their goal was to was save area, results don't seem that spectacular. 4 full P cores would fit and depending on clocks targets would provide benefits of homogeneous SoC at unknown at this point MT performance penalty.
Heck, 6P would not break bank either on this floorplan.

C-cores are there to increase efficiency as those are more efficient at low and moderate clock speeds. And AMD's solution is probably more homogeneous with hybrid design than with pure P-cores if hybrid design allows higher multicore clocks at low tdp use cases. But for mobility efficiency is at least as critical design point as performance and if they can achieve more battery run time with hybrid design they would be absolutely insane not to use it.

 

[bakyt115]

seems like zen4c cores bit wider (physically)

 

[JoeRambo]

C-cores are there to increase efficiency as those are more efficient at low and moderate clock speeds.

Are there any estimates at how their efficiency compares in server clocks region? While AMD surely can make Z4 use 20-30W per core, i doubt Z4C vs Z4 is that different when both are clocked say 3Ghz ? Not having full P cores is also opportunity cost due to lost peak perf in less TDP restricted regime. 2+4 just feel strange with this floorplan.
On topic of power saving i doubt they can touch Intel's approach of having E-cores outside of main chiplet. In AMD's case performance will be better ( the race to sleep part of "efficiency" ), but power draw due to uncore will be too.

 

[Joe NYC]

And as seen, both regular and C-cores share shame ring and L3-cache.

Which would be a good thing...

 

[naukkis]

Which would be a good thing...

Agree. But there was speculation before that p and c -cores are in different CCX with independent L3-caches - which would have made it much less efficient from performance view.

 

[Saylick]

Ugh, hope someone annotates this soon. THX.

Ask and yee shall receive.

From Twitter.

 

[eek2121]

Are there any estimates at how their efficiency compares in server clocks region? While AMD surely can make Z4 use 20-30W per core, i doubt Z4C vs Z4 is that different when both are clocked say 3Ghz ? Not having full P cores is also opportunity cost due to lost peak perf in less TDP restricted regime. 2+4 just feel strange with this floorplan.
On topic of power saving i doubt they can touch Intel's approach of having E-cores outside of main chiplet. In AMD's case performance will be better ( the race to sleep part of "efficiency" ), but power draw due to uncore will be too.

The v/f curve will likely be much different. You won’t be able to get “Zen4c” cores into 4ghz territory at all. They will be extremely efficient at the frequencies they do operate at. However, efficiency isn’t the reason AMD is including them, and I suspect we won’t see any hybrid “enthusiast” class chips…those will be all “big” cores. This is about competing with Intel Core i3/Core 3/Whatever Intel calls their chips these days. Maybe Core i5.

 

[eek2121]

Ask and yee shall receive.
View attachment 85606
From Twitter.

🔥🔥HOT! 🔥🔥

Nothing gets me going more than an annotated die shot of an unreleased product.

 

[Abwx]

The v/f curve will likely be much different. You won’t be able to get “Zen4c” cores into 4ghz territory at all.

They surely can clock way higher than 4GHz, and likely close to 5GHz, even if this pic is not correctly scaled it s obvious that they lose much less in frequency than what they gain in efficency :

Hot Chips 2023: AMD verrät wenig mehr über „Siena“ und verwirrt

Nach Genoa, Bergamo und Genoa-X fehlt noch Siena in AMDs Familie der Zen-4-CPUs für Server. Zur Hot Chips gibt es (verwirrende) Details.

www.computerbase.de

 

[bakyt115]

https://twitter.com/x/status/1700855408498245977

PHX2 review

 

[jpiniero]

They surely can clock way higher than 4GHz, and likely close to 5GHz, even if this pic is not correctly scaled it s obvious that they lose much less in frequency than what they gain in efficency :

From that PHX2 review the V/F curve is much worse on the dense core.

 

[BorisTheBlade82]

https://twitter.com/x/status/1700855408498245977

PHX2 review

Thanks for sharing.
I am a bit underwhelmed by the efficiency figures, to be honest.

 

[eek2121]

Thanks for sharing.
I am a bit underwhelmed by the efficiency figures, to be honest.

Density, performance, power. Pick 2.

If AMD could have designed the dense cores without compromise, none-dense cores would not exist.

3.0-3.5 ghz is going to be the sweet spot for these chips.

 

[Abwx]

From that PHX2 review the V/F curve is much worse on the dense core.

Those curves display the 8C 7840@17W as performing the same as the 6C 7540@13W, this should be the opposite, beside for the tested chip that s not definitive silicon but an ES with non finalized firmware, so one should be wary of those curious curves.

 

[JoeRambo]

They surely can clock way higher than 4GHz, and likely close to 5GHz

Yeah right:



It could be made worse by ES chip, but still i think, density must come with tradeoffs of V/F scaling, or otherwise Bergamo would not be limited to ~3Ghz boost.

 

[Abwx]

Yeah right:

View attachment 85637

It could be made worse by ES chip, but still i think, density must come with tradeoffs of V/F scaling, or otherwise Bergamo would not be limited to ~3Ghz boost.

Bergamo is limited by the sheer amount of cores and a 350W TDP.

As for this curve i wouldnt pay attention, as i pointed he s wrong in the previous one, not counting that it s a ES with no definitive firmware, the c cores are limited to 3.5Ghz and are fed with the voltage required by the regular cores to clock at close to 5GHz even if such a voltage is overkill for the c cores.

Edit : From the numbers at 3.5Ghz the c core is consuming 60% more than if it was to use the same voltage as a regular core, that doesnt make sense, even if it start from a lower power, beside VID is not the actual core voltage, there s the integrated voltage regulator that is in serial with this voltage.

 

[BorisTheBlade82]

Density, performance, power. Pick 2.

If AMD could have designed the dense cores without compromise, none-dense cores would not exist.

3.0-3.5 ghz is going to be the sweet spot for these chips.

Sure, but as per this review it is "pick one": Density.
So I am hoping this v/f curve is not the real thing as @Abwx suggested.

 

[jpiniero]

Phoenix U is available btw, but seemingly only the Pro SKUs. I think the 7540U might be the bigger die currently but limit 4 of the cores to the fmax of Little Phoenix.

 

[Abwx]

Mainstream "low cost" Epyc SKUs on sight :

AMD launches EPYC 8004 Sienna CPU series, up to 64 Zen4c cores and SP6 socket - VideoCardz.com

EPYC 8004 features up to 64 Zen4c cores AMD is launching a new series of its Zen4 processors. AMD EPYC Genoa, Genoa-X, Bergamo, and Sienna all share a common feature: they are powered by AMD Zen4 architecture and are strategically tailored to cater to the high-core count market segment within...

videocardz.com

 

[eek2121]

Phoenix U is available btw, but seemingly only the Pro SKUs. I think the 7540U might be the bigger die currently but limit 4 of the cores to the fmax of Little Phoenix.

AMD needs more tools for mobile tweaking. I can’t do anything with my Cezanne laptop, not even eco mode.

 

[Ajay]

AMD needs more tools for mobile tweaking. I can’t do anything with my Cezanne laptop, not even eco mode.

Well, OEM generally want laptops locked down pretty hard.

 

[moinmoin]

Mainstream "low cost" Epyc SKUs on sight :

AMD launches EPYC 8004 Sienna CPU series, up to 64 Zen4c cores and SP6 socket - VideoCardz.com

EPYC 8004 features up to 64 Zen4c cores AMD is launching a new series of its Zen4 processors. AMD EPYC Genoa, Genoa-X, Bergamo, and Sienna all share a common feature: they are powered by AMD Zen4 architecture and are strategically tailored to cater to the high-core count market segment within...

videocardz.com

Interesting, so Sienna is actually only using Zen 4c cores.

AMD needs more tools for mobile tweaking. I can’t do anything with my Cezanne laptop, not even eco mode.

Try RyzenAdj, it supports Cezanne as well (and a Windows built exists, too).

 

[Abwx]

Interesting, so Sienna is actually only using Zen 4c cores.

Guess that this allow a full set of advantages, competitively wise that s a no brainer.

The full slide deck can be found here, numbers are telling in matter of perf, perf/watt and cost advantage against Intel :

AMD Epyc 8004: Siena sorgt im Sockel SP6 doch noch für eine Überraschung

AMD machte bis zur letzten Minute ein großes Geheimnis aus Siena, nun ist bekannt warum: Die Server-CPU setzt doch nicht auf Zen-4-Kerne.

www.computerbase.de

 

[JoeRambo]

Bergamo is limited by the sheer amount of cores and a 350W TDP.

As 8004 series has shown us, the V/F curve of PHX2 might have been true. No matter the TDP, even 32C cores are not clocked above 3Ghz. They have like 2x watts per core headroom vs Bergamo, yet stay on 3Ghz max.
Even more is given away by base/boost clocks, not really going anywhere with increasing watts per core.

So pretty much the sweet spot is ~2.6Ghz and not only Zen4C can't clock 4-5Ghz like You've claimed above, it is not really efficient above 3Ghz either.