Yeah I thought SOC voltage was high enough - though that's not the case. But there's other ways to do linear regulators in efficient manner, maybe they just use depletion mode fets. That's pretty much 100% efficiency without voltage reduction between rails and still pretty good efficiency at voltage reduction even with common source. That's way better efficiency compared to switching power supply which needs close to 100% duty cycle to achieve full voltage to cores - where cores full power demand also exists.
Things are explicited in the pic you previously posted and that i reposted, the switching devices are namely Pfets, and since they are in serial with the positive rail it means that it s their sources that are connected to this rail, their drains are the outputs that feed the core, as such they are forcibly connected as common sources whatever the driving circuitry.Do you mean this?
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Iphone sales declining and Apple maintaining market share are not mutually exclusive. I dont know the full picture on revenue, unit sales Q on Q, etc so Im not saying which is the case, but just posting market share is not a full picture for sure.iPhone has NOT been declining as part of the overall smartphone market decline. You and Acid Rock are really living in some sort of universe of alternative facts because all you have to do is google and look up the market share percentages. The shipment volumes have declined slightly for Apple, but they can't increase every quarter especially with how much they had been increasing the last few years. People have been claiming the iPhone has peaked for like a decade now, and they are always wrong.
Not even accounting for the part of Apple only equipping non-mainstream (Pro/Max) iPhones with the new SoCs, cutting the # of wafer starts at ramp considerably.It's the percentage of revenue TSMC derives from smartphones vs. HPC.
Not too long ago, maybe 2 years ago, smartphones were majority of TSMC business. Last quarter, it was down to 33%.
So, the question is if Apple will continue to take majority of the leading node and continue to fund these leading nodes with Apple's orders. It's possible Apple's role will diminish.
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Do you suppose you could take this apple thing to the apple thread ?Iphone sales declining and Apple maintaining market share are not mutually exclusive. I dont know the full picture on revenue, unit sales Q on Q, etc so Im not saying which is the case, but just posting market share is not a full picture for sure.
It's not an apple thing, but a silicon allocation one and how it will affect node use by others.Do you suppose you could take this apple thing to the apple thread ?
…and yet Apple will sell a record number of iPhones within the next year.Iphone sales declining and Apple maintaining market share are not mutually exclusive. I dont know the full picture on revenue, unit sales Q on Q, etc so Im not saying which is the case, but just posting market share is not a full picture for sure.
Apple's the only one on N3E, no? Don't see how it relates to AMD when they won't be using the N3E production line. Ditto on Mark's words either way.It's not an apple thing, but a silicon allocation one and how it will affect node use by others.
It hasn't much to do with this IMO.…and yet Apple will sell a record number of iPhones within the next year.
I always laugh when people say Apple, of all companies, is done for. The most successful tech company. done. finished. Ignore the millions of units of Apple hardware sold every year. They are as good as bankrupt!
You folks are silly.
Apple is the only company using N3B. Zen5 is going to be on a mix of N4 and N3 according to their own slide from FAD 2022. (probably standard vs high density ('c') CCD).Apple's the only one on N3E, no? Don't see how it relates to AMD when they won't be using the N3E production line. Ditto on Mark's words either way.
Who's using N3E then? That charts correctly, dense is rumored to be on n3. dunno the epyc breakup if it's also a mix or mostly on 3.Apple is the only company using N3B. Zen5 is going to be on a mix of N4 and N3 according to their own slide from FAD 2022. (probably standard vs high density ('c') CCD).
AMD, NVidia, a lot of companies really.Who's using N3E then?
right I guess I mixed up my notes when I wrote them, and judging by the stains and scent that's a few months old, it was some kind of enriched wine, sherry if I had to guess.AMD, NVidia, a lot of companies really.
I brought apple up on context of nodes available in the zen 5 time frame and capacity at TSMC, which should be fair game.Do you suppose you could take this apple thing to the apple thread ?
Your silly because I never said any of that, and even went out of my way to state I was not saying that. I was merely pointing out that showing a market share graph is far from the whole story around production, sales, and profit.…and yet Apple will sell a record number of iPhones within the next year.
I always laugh when people say Apple, of all companies, is done for. The most successful tech company. done. finished. Ignore the millions of units of Apple hardware sold every year. They are as good as bankrupt!
You folks are silly.
…and yet Apple will sell a record number of iPhones within the next year.
I always laugh when people say Apple, of all companies, is done for. The most successful tech company. done. finished. Ignore the millions of units of Apple hardware sold every year. They are as good as bankrupt!
Cpu does not increase clocks like that. It first request voltage and only increases it's clocks after voltage have risen. Also Cpu can't alter base PLL for frequency changes, they can only change multiplier against that base clock.Things are not done randomly, a big advantage of a PWM output is that the duty cycle can be tied to the PLL that generate the base core clock, this way as the core frequency increase so does the duty rate of the mosfets that output the core supply voltage.
I wasn’t singling any one person out, merely mocking the folks that claim Apple is no longer relevant. Apple is one of TSMC’s biggest customers. If they moved to Samsung or IFS tomorrow heads would roll with TSMC and you would see a considerable decrease in revenue, possibly leading to TSMC posting multiple losses in the quarters moving forward.Your silly because I never said any of that, and even went out of my way to state I was not saying that. I was merely pointing out that showing a market share graph is far from the whole story around production, sales, and profit.
Cpu does not increase clocks like that. It first request voltage and only increases it's clocks after voltage have risen.
That AMD's in-core voltage regulation has one design point zero voltage drop which is always used at least for one core. For switching power supply that use scenario is it's lowest efficiency point - for linear regulator it's the most efficient.
I have bad news for you since Dense CCD is only weeks after normal CCD and it's on N3e.I wasn’t singling any one person out, merely mocking the folks that claim Apple is no longer relevant. Apple is one of TSMC’s biggest customers. If they moved to Samsung or IFS tomorrow heads would roll with TSMC and you would see a considerable decrease in revenue, possibly leading to TSMC posting multiple losses in the quarters moving forward.
As far as how this relates to AMD. Some here are saying AMD is using N3 (note the lack of a variant listed) for Zen 5, but there has been at least 1 AMD slide stating N4 | N3. This leads me to believe that either plans changed (not likely) or Zen 5 will be on N4/N4P, while dense and possibly mobile variants will be on some form of N3. I am not convinced desktop Zen 5 will be on N3.
I could be wrong of course. The person I knew at AMD left the company a while back so I have nothing except speculation, same as you all.
The timing does not add up for any of it. This is what I know:
Knowing that, and also given some other unverified claims I have seen of a 1H 2024 release, I don’t see how they could possibly use anything except N4 for desktop/server. I believe N3 will absolutely be used for Zen5c and possibly mobile where those energy/density savings are absolutely needed.
- AMD shows off slides mentioning N4 | N3 as well as “advanced node” for Zen 5.
- Apple rumored to be buying up all of N3 for the next-gen iPhone/iPad/Mac launches.
- Intel also rumored to be buying up tons of N3 capacity
- AMD has a tendency to NOT push node shrinks early on. They are currently using N4 for mobile and N5 for desktop.
- AMD’s goals are margin and revenue focused. N3E is new and much more expensive while not offering much compared to N4/N4P. Sure, there is a shrink and savings to be had, but Zen 5 is going big.
- Zen 5 is a brand new architecture. Previously with Zen 3, AMD stuck with the same node for the rebuild.
- AMD design choices appear to be iterative rather than revolutionary.
I was wondering when you'd say something about that. yes like amd is gonna sit on zen5c/dense doing nothing but twiddling their thumbs.do you know if zen 5 will reuse the same igpu layout gen for z5 like z4?I have bad news for you since Dense CCD is only weeks after normal CCD and it's on N3e.
Please stop talking about things you have no idea of.
How is it sandbagged when there's no real noticeable performance difference seen?It's nice to see AMD was sandbagging with the Memory speeds. It looks like with the new AGESA bios update DDR5 8000mhz is supported.
Before Zen 4 was released. AMD said Zen 4 memory would really shine in over clocking. After the Zen 4 release, people were scratching their heads because even 6000mhz was an adventure getting the memory stable. I said sand bagging because the newest bios removes memory restrictions making 8000mhz DDR5 memory possible.How is it sandbagged when there's no real noticeable performance difference seen?
You're talking about what Geppetto from amd said, aka the bald twat who later resigned. I remember such a statement but it was about getting out of 1:1 ram sync for the fclk and if. 8000 takes it out of it as I understand. the benefits are minimal compared to an intel ks processor capable of hitting high 7000 or low 8000 oc compared to 6400.Before Zen 4 was released. AMD said Zen 4 memory would really shine in over clocking. After the Zen 4 release, people were scratching their heads because even 6000mhz was an adventure getting the memory stable. I said sand bagging because the newest bios removes memory restrictions making 8000mhz DDR5 memory possible.
We are still a year away from low latency DDR5. There is room for improvement. It's going to take more time.
It's not a trivial problem. There's two different voltage regulators in series where both of them can affect voltage rise times. And it's documented, AMD have used years system that regulates core clock by actual delivered voltage - it's absolutely needed scheme to drive voltage margins down. AMD LDO is natural evolution step on that regulation scheme - after shaving voltage margins for all cores they also shaved those per core basis.Frequency increasement can be delayed by a given amount of cycles the time it takes for the LDOR to reach the nececessary voltage, that s trivial problem here.