Given the history of Zen cores so far I wouldn't expect them to be tied down to any single node.I thought Zen5 was on TSMC 4nm?
I was merely considering the launch desktop node, not laptop, dense cores or future revisions of the design.Given the history of Zen cores so far I wouldn't expect them to be tied down to any single node.
Zen1 had 2 nodes (at least), Zen2 had 2 (possibly more depending on what node PS5 Pro SoC is fabbed on), Zen3 had 2 and we're probably still not at the end of Zen4's lifecycle yet, so it may be on more than 1 node also.
I wouldn't at all be surprised to find Zen5 being fabbed on more than one node during its lifecycle considering its significant departure from current core design.
Ah so definitely N5 and N4 then.Straight from the horse's mouth (you may call him AMD):
5950X: TSMC 7nm FinFET
7950X: TSMC 5nm FinFET
5900HS: TSMC 7nm FinFET
6900HS: TSMC 6nm FinFET
7940HS: TSMC 4nm FinFET
8945HS: TSMC 4nm FinFET
5900HX: TSMC 7nm FinFET
6900HX: TSMC 6nm FinFET
7945HX: TSMC 5nm FinFET
5850U: TSMC 7nm FinFET
6850U: TSMC 6nm FinFET
7840U: TSMC 4nm FinFET
8840U: TSMC 4nm FinFET
7545U (with Zen4c cores): TSMC 4nm FinFET
No, it's the same node (more or less).So, will we see a greater uplift in MT than in ST as they move from 5nm to 4nm?
So are these numbers still somewhat correct?No, it's the same node (more or less).
The shrink party is over until N2p-ish.
But bunch of us are not engineers (well sort of in my case) and we stopped dealing with the iso term the moment burning DVDs went out of fashionYep. This use of the prefix "iso" to mean "same" is very common in engineering. I typically deal with isothermal (same temperature), isotropic (same physical properties), isocontour (same line or surface on a plot), etc.
But ISO files are still around and sometimes you may need to mount themBut bunch of us are not engineers (well sort of in my case) and we stopped dealing with the iso term the moment burning DVDs went out of fashion
Yeah, something is changed in an official/marketing language since then. This quote is from ISSCC 2020 / February 17, 2020:AMD zen 3 ISSCC
A principal objective for Zen 2 was to deliver better performance/W compared to
the previous-generation design. Zen 2 silicon is running at frequencies
comparable to Zen (Fig. 2.1.7), while delivering substantial performance and
power improvements through a combination of architectural IPC enhancement,
physical design methodology, and macro improvements which exploit 7nm
technology.
So current Genoa Epyc IO die has 16x GMI with 4 not used in any current parts?Consoles really don't need that, they're not laptops.
It's for always online background downloads stuff without the usual horrible hacks.
It's a tricky challenge yeah.
Yea it's the same and very basic still.
Fancypants packaging is all Venice gen parts.
No, Turin gets a new sIOD with more IFOPs, faster mem and CXL2 support.So current Genoa Epyc IO die has 16x GMI with 4 not used in any current parts?
How’d you know it’s coming out in April?Must be nice for folks to be able to order their Zen 5 CPUs in April, with an awesome 32% IPC bump. Too bad for the clock regression and the 999USD price point for top end. It s just a few weeks before the reviews hit your favorite YTer.
AMD APU codename?
Strix A0(7nm) / Sarlak (7nm) / Strix B0 (7nm) / Kraken(5nm) / Sound wave(3nm)
Strix and Kraken are APU products confirmed in existing rumors, so other products are also assumed to be APUs.
Stirx A0, B0 are believed to be the rumored Strix Halo (chiplet) and Strix Point (monolithic).
I don't know which one is A0 or B0. (But there are also rumors that Sarlak is a Strix Halo.)
In the rumor, both Strix and Kraken are 4nm, so the difference from 7nm is large, so the reliability of the process indicated here should be considered low.
If you focus on the specifications, it is likely that they are all Zen5 and RDNA3.5 specifications.
Strix, Sarlak, Kraken IO dies.
It can be confirmed that the three products have a chiplet structure.
The product would have been marked as having a chiplet structure, but considering that Strix and Sarlak were marked separately, there is a high possibility that the rumor that Sarlak = Strix Halo is not true...
There is room for interpretation that the three products use the same IO die, but since the IO die also includes a GPU, looking at the GPU specifications alone, this seems unlikely.
Looking at the rumored roadmap, it is tied to the same lineup as monolithic Strix and Kraken, and the monolithic Strix GPU is 16CU.
The chiplet Strix GPU specifications are known to be 40CU, but if you look at the Kraken GPU specifications as 16CU, the difference is too large to cover with a cut chip.
I guess he's just satirized the rumor mill about the Zen5 recently.How’d you know it’s coming out in April?
dunno what is "packaging". OTOH, not only single source were complaining the Zen5's slower-than-expected progress, looks like there must be something happened. Some supply chain/factory did received orders related to Zen5 not too long ago but progress was slow. Don't ask the exact release date or perf number, I saw some "people in the know" also feel shocked why perf number is not leaked yet.ZEN5 desktop start mass packaging next month
This is roughly speaking:dunno what is "packaging"
I saw some "people in the know" also feel shocked why perf number is not leaked yet.
Let me guess. The 1st?Must be nice for folks to be able to order their Zen 5 CPUs in April, with an awesome 32% IPC bump. Too bad for the clock regression and the 999USD price point for top end. It s just a few weeks before the reviews hit your favorite YTer.
That thread also says (after google-translating to English):
You're right. Author's narrative feeling like it's the last step of a CPU being made, possibly IHS/LGA related.This is roughly speaking:
Packaging is everything that isn't the actual semiconductor lithography in chip manufacturing.
- Bonding various dies to the substrate.
- Adding the IHS on top.
- Adding the traces for the LGA bumps.
- Bonding the LGA bumps themselves.
The most useful information were from thread's author, also the admin of that forum. The rest of the posts by others are just speculation.That thread also says (after google-translating to English):
Had to google that. Chinese Epyc. I suppose it's castrated?”The zen5 conference may be the release of Ryzen and Xiaolong at the same time. The Xiaolong will be distributed in advance, and the Ryzen will be delayed by 1-2 months.”