Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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NTMBK

Lifer
Nov 14, 2011
10,242
5,035
136
While PHX suffers from being RDNA 3 bound and thus has generally poor idle.
MTL is really an impressively poor thing, considering that it's meant to be an "all of our engineering skills went into this" product, tiles, packaging and all the good things Intel could do with it.
9 months later too...
Intel put all their exciting new ideas into one product, just like with Pentium 4!
 

StefanR5R

Elite Member
Dec 10, 2016
5,539
7,875
136
I may be odd, but this is the first question which comes to my mind when I see a vendor presenting Geekbench charts:
Do they still lack a toolchain which can compile the SPEC CPU suite?
 
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CakeMonster

Golden Member
Nov 22, 2012
1,393
501
136
Lots of early bugs in the BIOS'es with the new AGESA that supposedly support Z5. On the Asus forums, beta releases have fixed a few of them, like not being able to disable the IGP, but the M2 drives randomly disappearing is still an issue on the latest versions reported by several users.

I think new drivers and BIOS'es makes it quite obvious that something is happening, crossing fingers that the state of firmware and drivers on release is less bumpy than for Z4. The only bug I still experience with Z4 is occasional crackling on BT audio.
 

BorisTheBlade82

Senior member
May 1, 2020
664
1,015
136
Power is function of Voltage squared. Which is also shown in the formulas.
I think, no one argues that. But besides @FlameTail getting even his simplified function terribly wrong there applies a certain additive offset and the curve might not be as steep in every interval. Much more so, when we talk about SoCs that have a looooot of uncore with a rather static consumption.

This is a measurement I already posted here several times in the past. It is from my own AMD 4700U Renoir. Look at the blue line, which is the duration of a CB23 run (secondary axis): Below 12w Package Power, the performance increase scales more than linear with power - the reason for a big part of this is the uncore consumption.

 

Tuna-Fish

Golden Member
Mar 4, 2011
1,357
1,565
136
Actually, better question: if widening the cores is just free efficiency at any frequency, why don't we have 10/12/14 wide decode?

Two big reasons:

Firstly, the cost of widening variable width decode is not linear, but exponential. This is the one big advantage that 64-bit ARM has on x86, they can just decide how wide they want their decode to be and duplicate the units, x86 has to deal with first finding out where the instruction boundaries are and then muxing data from the correct offset to every decoder. It's notable that both major x86 vendors use designs where they have a wider path from (fixed-width) uop cache and narrower decode.

Secondly, as noted upthread, jumps are too frequent. Monolithic very wide decode will just waste power decoding instructions that are not going to be executed. One solution to this is the very interesting split decode (2x3) implementation in Tremont, I believe AMD has some patents that describe a similar design.
 

Mahboi

Senior member
Apr 4, 2024
347
589
91
Two big reasons:

Firstly, the cost of widening variable width decode is not linear, but exponential. This is the one big advantage that 64-bit ARM has on x86, they can just decide how wide they want their decode to be and duplicate the units, x86 has to deal with first finding out where the instruction boundaries are and then muxing data from the correct offset to every decoder. It's notable that both major x86 vendors use designs where they have a wider path from (fixed-width) uop cache and narrower decode.

Secondly, as noted upthread, jumps are too frequent. Monolithic very wide decode will just waste power decoding instructions that are not going to be executed. One solution to this is the very interesting split decode (2x3) implementation in Tremont, I believe AMD has some patents that describe a similar design.
Wow, thank you, very complete response.
 

PJVol

Senior member
May 25, 2020
539
451
106
Actually, better question: if widening the cores is just free efficiency at any frequency, why don't we have 10/12/14 wide decode?
Because it's not free, at least? What are you gonna do, for example, with the supposed 30-40% Cac increase for a wider core, or with the corresponding increase in clock mesh power? To even get close to the efficiency of the previous gen's they have (had?) a hell of a lot to optimize
 
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Mopetar

Diamond Member
Jan 31, 2011
7,875
6,115
136
You might not take the branch the first time, but if you do eventually, the wider decode will have already added the instruction to the micro-op cache so that it's there the next time around. A lot of code is looped so the one-off branches are going to be a minority.

The bigger pain will just be having to deal with the variable-length instructions. Having a wider decode might make it a little more likely that the full instruction is there and let compilers that want to optimize have an easier time of aligning everything in memory.
 

Hans Gruber

Platinum Member
Dec 23, 2006
2,141
1,090
136
We already know Zen 5 is going to be good. The question, does it need to be great to beat Arrow Lake. Releasing Zen 5 early would mean Zen 5 would be number #1 across all performance metrics like Zen 3 was for a handful of months at minimum. I just wish AMD would offer a 24C or 32C product in the Zen 5 product lineup. The AMD playbook was supposed to be a core war with Intel. Ryzen has been at 16 cores since Zen 2.
 
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