- Mar 3, 2017
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CES'25.Halo is expected for 25Q1? Q2? Did it change with the recent rumor of Zen5's simultaneous rollout across the lineup?
Yeah they basically rolled DT/luggable parts into mobile instead of server.Either way, I am starting to see what you mean about multiple chips w/ different configs but sharing the same IP.
and which is desktop ? losing track....I think he already shared the timeline for Z5 rollout, no? iirc:
May/June - Strix Point (Could be MS AI build event or Computex). Release in July or August
June - GNR (Computex). Release in Q3/Q4
Jan - Kraken Point and Strix Halo (CES 25). Release in Q1 25
Sonoma is ???. But probably isn't that long given it's a socket upgrade over Mendo.
GNR is desktop.and which is desktop ? losing track....
GNR and STX1 are both June 3rd.May/June - Strix Point (Could be MS AI build event or Computex). Release in July or August
June - GNR (Computex). Release in Q3/Q4
Jan - Kraken Point and Strix Halo (CES 25). Release in Q1 25
That is exactly what I wanted, thanks !GNR and STX1 are both June 3rd.
The former is July, the latter is August.
Apparently it’s Strix Point.
1st this the 1st benchmark or have we seen this earlier.
No.
Useful for laptops tho, can cache display/media hits.
yea that's the stx1 OPN.Apparently it’s Strix Point.
No.I wonder if Venice has MALL...
MI300 has MALL ot make it all work.But that could be different in server if there are some 8-16 CCDs potentially hitting the memory attached, such as potential Mi300c or potentially Venice.
and which is desktop ? losing track....
it is. should be SF4X or something.Sonoma is apparently very low end mobile, 0x Zen 5 + 4x Zen 5c cores, also with smaller iGPU. There are some rumors it might be fabbed by Samsung Foundry.
Could be spoofed results, I would be wary too, never know. Also its virtualized.So weird all the talks about ipc seemingly vanished overnight, as if the actual results are now in the wild and people have to be quiet about it. Weird.
It can, look at the .gb5/.gb6 result database for anything with Xen hwvirt string.Or could be GB5 cannot read the frequencies properly inside Xen
but how?
two 8 core CCDs!
So you are suggesting 16C Zen6 will have better MT perf than Arrow Lake Refresh 8P+32E?16 big cores. You don't need anything more!
Yeah, mobile includes luggables/mobile WS/halo all that stuff.
So Zen6 DT will use same SOC tile as Zen6 Halo?SOC tiles share the IP, but not configs.
Mobile and luggables use different SOC tiles.
It doesn't have to.So you are suggesting 16C Zen6 will have better MT perf than Arrow Lake Refresh 8P+32E?
They can get Threadrippers.then persons primarily needing max MT perf should get Arrow Lake Refresh instead of Zen6?
How did you even come to this conclusion.So Zen6 DT will use same SOC tile as Zen6 Halo?
Not for your use cases perhaps, but for others. More specifically those that need max MT perf on DT at a reasonable price. Sounds like Arrow Lake Refresh will be a better option for them, if there will not be any Zen6 DT variant to counter it.It doesn't have to.
Or EPYCs. But they are not reasonably priced (for most persons using them for private use). Arrow Lake Refresh 8P+32E should be much cheaper compared to lower end Zen6 Threadrippers, for those looking for max MT perf in that range.They can get Threadrippers.
Well, you're statements were not 100% clear, so I had to make some guessing.How did you even come to this conclusion.
But are you suggesting DT will share dies with mobile?
So Zen6 DT will at least share SOC tile with one of those as I assume it.Yeah, mobile includes luggables/mobile WS/halo all that stuff.
People that need nT have money.More specifically those that need max MT perf on DT at a reasonable price
People that need nT have money.But they are not reasonably priced (for most persons using them for private use)
Reading and bracketing adjacent market segments isn't hard at all.But if Zen6 DT will not share SOC tile with Zen6 Halo, then which mobile Zen6 variant will it share SOC tile with? Or are you suggesting Zen6 DT have it's own SOC tile only used on DT after all?
Ghostsonplanets mentioned that it's likely that Zen 6+ starts dividing between TSMC eVLT and uVLT (differences in performance and power at low usage). Most likely with Zen 6c using the lower power stuff and ending up on mobile.To summarize, Zen 6 things should be pretty clear by now I hope...
- Will use CCDs + IOD for pretty much the entire client stack, from ultrabook chips to mobile workstations to desktop. CCDs remain the same, but IOD will differ depending on product.
I'm not super sure that CCDs can be shut down correctly, can't remember where I mentioned shutting down cores but I was basically told "nah, rebooting/resyncing is making an unacceptable latency". Although that was for GPU and memory so maybe that doesn't apply so much on CPUs but I doubt that you can entirely shut down CCDs. I wonder about a really low power mode though.- Mobile IODs will have Infinity Cache and varying levels of iGPU and NPU performance depending on the use case. I hope that mobile IODs have a low power core so that the CCDs can be shut down in period of low activity.
Isn't Strix Halo precisely the contrary? I think Uzzi mentioned that it's sort of the basis for DT's future.Desktop IOD won't have the Infinity Cache or an NPU but likely keeps a small iGPU for basic display purposes.
Yay N31 redemption arc- Infinity Fabric over CoWoS-R is what connects the CCDs to IOD. This should be pretty similar to what N31 uses.
What about those Z1/Z1 Extreme type SKUs? Those are mixed, I don't see why they would stop? Even Kraken is mixed IIRC.- No mixing and matching of CCDs regarding Zen 6 Classic/Dense. CCDs are all Zen 6 Classic.
I doubt that they'll drop 3D V$ anytime soon. On the contrary, it may well become a "forever" staple of all x86 vendors.- My guess is that the Zen 6 CCD will likely still support 3D V-cache. You'll get V-cache in desktop. No idea if you'll get it on mobile.
Why would it?So Zen 5 Desktop is confirmed to be 16-core max on desktop, with no Zen5c variants coming to AM5
Does Zen 6 push past the 16-core Desktop limit on AM5 ?