AMD “Next Horizon Event" Thread

[Abwx]

C-Ray is very favorable for Zen.

Still, there s 64C and likely that scaling is not 100% from 56C, the Xeons run at 2.7GHz while the Epycs are at 1.8-2GHz, indeed from the perfs improvements displayed it seems that they will be base clocked like their predecessors in the 2-2.2GHz range.

 

[Despoiler]

I'm leaning towards 1 since the shape of the die is much less rectangular, and 1x CCX should be more space efficient.

Pros and cons to both ways. It's a lot of IF links if they keep doubling in the current system which in turn adds power and keeps most of the cons of the current Zen. Getting to 8 core CCX means fewer chips per wafer, but it might not matter that much. Workloads are more likely to sit on fewer CCX. It also would mean that Zen 2 consumer would deliver monolithic like performance because it has 8 cores to go to an I/O. No bouncing between CCX.

 

[HurleyBird]

Going to 8 core CCX likely means more chips per wafer, since a single complex can be more compact versus spreading out to multiple complexes.

 

[itsmydamnation]

Going to 8 core CCX likely means more chips per wafer, since a single complex can be more compact versus spreading out to multiple complexes.

How is routing going to work, the L3 currently is a sliced and hashed on lower order bits.

 

[csbin]

Still, there s 64C and likely that scaling is not 100% from 56C, the Xeons run at 2.7GHz while the Epycs are at 1.8-2GHz, indeed from the perfs improvements displayed it seems that they will be base clocked like their predecessors in the 2-2.2GHz range.

8180m@3.2G all core(Non AVX)，2.8G all core(AVX2)

 

[William Gaatjes]

It makers me wonder what the DF /IF data transfer bandwidth and clockspeed will be between the chiplets and the IO die.

 

[Doom2pro]

The latest image of the chip

And that center die looks only moderately larger than Zeppelin, just a bit wider... Look how small those core dies are.

 

[PeterScott]

The latest image of the chip

And that center die looks only moderately larger than Zeppelin, just a bit wider... Look how small those core dies are.

The biggest mystery is why the chiplets are paired off. Very strange.

 

[dnavas]

The biggest mystery is why the chiplets are paired off. Very strange.

...to match cooling solutions for Naples? Looks like the pairs are in approx same place as dies?

 

[amd6502]

It's really odd how close the chiplets are. If it were for thermal reasons only they'd surely be further apart?

It's to make the glue stick better.

 

[PeterScott]

Just putting them together. The chiplet pairs are kind of emulating the outer regions from the dies on Naples:

 

[William Gaatjes]

The biggest mystery is why the chiplets are paired off. Very strange.

Perhaps it is likely that there is some sort of crossbar between paired chiplets. To get 4 nodes of 16 cores. Perhaps how the 4 cores in a ccx are connected, the 4 ccx themselves are connected in the same way. To get a low latency connection between 16 cores. The chiplets perhaps share the L3 between them as one large L3. Not only using the two lowest bits , but now the three(8) or four(16) lowest bits.
4 of those 16cores / 4ccx nodes would make 64 core behemoth.

 

[teejee]

The biggest mystery is why the chiplets are paired off. Very strange.

The pinout of SP3 is very likely adapted to EPYC 1 so my guess is they keep the same layout to better match the pinout for the SP3 socket and reduce the complexity of the module.
Especially the power pins should go directly into the silicon.

 

[Tuna-Fish]

My bet for the overall system architecture:

The cores in each chiplet are logically equidistant, that is, in one CCX. The L3 is 32MB and equally reachable from all cores, with lines hashed to the cache slices by the lowest bit of line addresses. It is not radically faster than Zen L3, and might actually be a bit slower. 30 cycles is already very fast for a 8MB cache, and while the shrinking transistors help speed, quadrupling size is going to hurt it.

There is a huge L4 that is memory side (that is, it only holds data from the memory channels connected to the die). It either is fully inclusive of all the data read from attached memory channels, or has enough extra tags so it at least holds tag entries for all cache lines held from those areas of ram. This allows it to manage all the coherency for multi-socket systems. The size of that L4 is probably 512MB, because the very first leak that mentioned 8+1 dies said that.

The fact that the chiplets are paired up is a red herring, for compatibility with existing cooling solutions or something. There is no data connection between those dies, except through the IO die.

 

[moonbogg]

AMD will be more competitive during the next couple years than they currently are. This has been my safe fortune-cookie take on the situation.

 

[dnavas]

Stupid question -- the system diagram labelled eight DDR channels, there's a slide that calls out competitive memory bandwidth, but latest Intel chips seem to be aiming at 12 DDR channels. So ... is the system diagram not to be taken literally and there will be a non-compatible offering with more, or ???

 

[Abwx]

Actual results of the C-Ray bench.

1 x Epyc 2 64C 27.7s
2 x Epyc 7601 28.1s
2 x Xeon 8180M 30.5s

https://www.computerbase.de/2018-11/amd-epyc-rome-64-kerne-9-chip-prozessor/

 

[moonbogg]

Is 3 seconds a big deal? I honestly don't know.

 

[Abwx]

Is 3 seconds a big deal? I honestly don't know.

The Epyc 2 64C consume the same as a single Epyc 7601 or a single Xeon 8180M, you re right, 2x the perf/watt is not that big a deal...

 

[dnavas]

Stupid question -- the system diagram labelled eight DDR channels, there's a slide that calls out competitive memory bandwidth, but latest Intel chips seem to be aiming at 12 DDR channels. So ... is the system diagram not to be taken literally and there will be a non-compatible offering with more, or ???

Buried in the endnotes I see that the "competitive memory bandwidth" is a comparison of currently existing processors, and "Memory bandwidth with 'Zen 2' design parameters including increased memory speed across eight memory channels."
slide 138 of 140.

So, there's how Intel will compete -- bandwidth heavy computations will likely stick with Intel's CascadeLake. The good news is that there appears to have been work done on memory speeds. How much is now the question.

 

[mattiasnyc]

The Epyc 2 64C consume the same as a single Epyc 7601 or a single Xeon 8180M, you re right, 2x the perf/watt is not that big a deal...

Not everything is sarcasm, irony or rhetoric. I was wondering the same thing since I only glanced at it briefly, and your answer regarding efficiency is appreciated... the snark though... or am I reading it wrong?

 

[inf64]

Also we don't know what kind of compiler optimizations were used for Zen2's improved FP units (if any) and Zen2's operating frequency. Something tells me in one years time frame Rome will crush everything in this benchmark.

 

[Abwx]

Not everything is sarcasm, irony or rhetoric. I was wondering the same thing since I only glanced at it briefly, and your answer regarding efficiency is appreciated... the snark though... or am I reading it wrong?

Well, the first thing that comes to mind when transitioning from 32 to 64C is wether they could keep the same power envelloppe, even at same frequency that s not that obvious, but here that s the case and was stated during the conf, hence why i was somewhat harsh...

AMD insisted on the perf/watt improvement, and for a reason as it seems that TSMC process is first geared toward low power rather than high frequency, the perf/isopower and power/isofrequency ratios given by Mark Papermaster point clearly in this direction.
They ll grab something due to the smaller node, but not sure that GF s 7nm wouldnt have been better at least for higher Fmax.

https://www.anandtech.com/show/13547/amd-next-horizon-live-blog-starts-9am-pt-5pm-utc

 

[amd6502]

This strategy towards 7nm is creative, bold, and pretty brilliant if it works. I don't think anyone saw this coming.

Moving the memory controller off the CPU die has implications that for desktop the memory controller will go into a GPU die. So dGPU production (at ~20 CU) will equal iGPU production for HEDT. This could for example make an enthusiast edition to succeed 2400g, as well as be the next gen successor of Polaris 11.

So to add to mainstream/budget RR APU we might see either/both a TR5 APU and an AM4 APU with HBM, such as seen in fengHuang APU.

 

[JDG1980]

AMD insisted on the perf/watt improvement, and for a reason as it seems that TSMC process is first geared toward low power rather than high frequency, the perf/isopower and power/isofrequency ratios given by Mark Papermaster point clearly in this direction.
They ll grab something due to the smaller node, but not sure that GF s 7nm wouldnt have been better at least for higher Fmax.

We don't know what the shipping clocks for Zen 2 products will be, but we do have some figures released for Vega. The existing Radeon MI25 (Vega 10 @ GloFo 14nm) has a peak boost clock of 1500 MHz. The upcoming Radeon MI60 (Vega 20 @ TSMC 7nm), announced today, has a peak boost clock of 1800 MHz. This reflects a 20% clock speed increase at the same TDP (300W for both cards).

The original Zen on GloFo 14nm tops out at about 4.0 to 4.1 GHz (the "12nm" process which is really a tweaked and refined 14nm can do a few hundred MHz above that). Interpreting the process gains based on what we've seen announced with Vega so far, this would indicate to me that we're probably looking at peak boost clocks of 4.8 to 5.0 GHz for consumer-focused Ryzen 3000 products. Of course, server EPYC CPUs are going to be running at considerably lower clock rates that optimize for perf/watt rather than raw maximum power.