Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[uzzi38]

Have we seen any indication yet that Intel is preparing an 8+16 Meteor Lake CPU tile?

All of the things shared by Intel thus far have been either with either a 2+8 or a 6+8 die afaik.

 

[lightisgood]

"Meteor Lake and Arrow Lake chips will scale to meet the needs of the mobile and desktop PC market, whereas Lunar Lake will serve the mobile 15W and under market."

The chiplets and interposer are wired together with TSV connections, and the interposer doesn't have any logic.

The Meteor Lake base tile is different than the one found in Lakefield, which served as an SoC of sorts.

The 3D Foveros packaging tech also supports active interposers.

Intel says it manufactures the Foveros interposer with its low-cost and low-power-optimized 22FFL process (the same as Lakefield).

I think that passive base tile largely has two benefits.

1st:low-cost, 2nd:high-scalability.

So, MTL family could have the "8P + 32E" compute tile.

Similarly, They could have 256EUs (128EUs*2 or 256EUs*1).

 

[dullard]

All of the things shared by Intel thus far have been either with either a 2+8 or a 6+8 die afaik.

Intel has been showing a lot of their cards. But this particular card they have held closely to themselves. Intel could put a lot of cores onto Meteor Lake, or not. I personally think Meteor Lake desktop is just a temporary stepping stone towards the much more powerful Arrow Lake desktop. But, I could be wrong.

 

[moinmoin]

I meant the fact that it was even on N3 to begin with, and the only reason it was ever accepted by fact is this incredibly misleading slide from Intel which was displayed earlier this year:

View attachment 66361

Intel should have listed 22nm, N6 and N5 and whatever other nodes ARL will use as well just to be actually all encompassing. /s

Glad it's finally cleared up. Looking forward to seeing what Intel will do with the flexibility won through this approach. I'm hoping for some positive surprises. Or will those be limited to Lunar Lake?

 

[Tech Junky]

Meteor Lake desktop is just a temporary stepping stone

Seems a lot like 10/11th gen being uneventful compared to ADL/RPL having significant boosts in performance. I skipped 10/11 knowing ADL would blow them out of the water with features. It didn't make any sense to waste the time or money rebuilding for them. The same goes for MTL as the real punch is going to come with ARL. The shift is significant skipping the odd releases at this point. They're just placeholders to keep up with the market being able to say it's the latest generation for marketing and consumers gobble it up.

ARL and beyond should be worthwhile though but, there's so much unknown events taking place in the surrounding areas of tech that impact how the CPU might perform or implement those additional technologies. Considering the leap from PCIE >> PCIE in only a couple of years makes me wonder if we'll be seeing additional leaps forward in that realm as well WIFI7 making an impact on the the networking side.

For instance they just released a CNVIO2 / AX411 with dual connect that uses 2.4/5 bands simultaneously to speed up aggregate bandwidth for single 2x2 clients. With the AX210 it performed fine but, with the AX411 I'm hitting closer to the max speed afforded by 160mhz channels which would be 70% of 2400mbps which is 1700mbps and routinely getting 1500mbps from the new card.

There's also talk about Thunderbolt 5 coming soon which will be more lane / BW intensive doubling the speeds to 80gbps. There's just so much stuff that ties into the equation to really assess what will come to fruition and when due to how OEMs have to apply them to the board based on the specs from Intel and all other parties.

 

[igor_kavinski]

Is it possible that the SoC tile has a large amount of cache to act as a buffer to hide the increased latency due to going with the chiplet approach?

 

[Joe NYC]

Is it possible that the SoC tile has a large amount of cache to act as a buffer to hide the increased latency due to going with the chiplet approach?

Could be system level cache.

 

[lightisgood]

Is it possible that the SoC tile has a large amount of cache to act as a buffer to hide the increased latency due to going with the chiplet approach?

IMO, it is not critical either monolithic/tile arch.

#c.f. Sapphire Rapids maintains the traditional mesh topology.

Thanks to ring topology, Xe-LP@TGL can rely on (up to) 12MiB CPU's SRAM as VRAM.

But MTL's bus topology must be changed.
So, Xe-tile@MTL can't do it.

This is why, MTL's SoC tile could have large SRAM area combining CPU's L4$ and VRAM.

On the other hand, optional-memory-tile, by Co-EMIB, might be more better implementation for the large SRAM (or eDRAM) area.

 

[SteinFG]

Took intel's 6+8 soc layout and scaled it to the same scale as 2+8. 6+8 looks a lot bigger. Bigger CPU, IO die, GPU, and interposer. So intel will make a different foveros interposer for each layout I assume? kinda non-modular.

 

[SteinFG]

And so if this gpu tile is really just 2x the cores, then this explains one of Intel's meteor lake slides which said 96-192eu. It's 92eu for 2+8 config, and 192eu for 6+8 config

 

[Exist50]

And so if this gpu tile is really just 2x the cores, then this explains one of Intel's meteor lake slides which said 96-192eu. It's 92eu for 2+8 config, and 192eu for 6+8 config

Reasonably sure those numbers where wrong, and it's 64/128.

 

[SteinFG]

Reasonably sure those numbers where wrong, and it's 64/128.

It would be weird to offer only 64eu on 2+8 version because intel already offers 96eu on 2+8 alderlake models, so this would be a step backwards.

 

[Exist50]

It would be weird to offer only 64eu on 2+8 version because intel already offers 96eu on 2+8 alderlake models, so this would be a step backwards.

Well the EUs would be significantly better, so there's zero chance of a performance regression, but I agree that it looks odd on paper.

 

[IntelUser2000]

And so if this gpu tile is really just 2x the cores, then this explains one of Intel's meteor lake slides which said 96-192eu. It's 92eu for 2+8 config, and 192eu for 6+8 config

That makes little sense since 2+8 needs the fastest iGPU like now. Otherwise they would be even less flexible.

Intel can easily make half a dozen different versions, and they did that with monolithic dies!

 

[uzzi38]

That makes little sense since 2+8 needs the fastest iGPU like now. Otherwise they would be even less flexible.

Intel can easily make half a dozen different versions, and they did that with monolithic dies!

Each new combination needs a new base tile. This should be relatively easy to do - it's produced on 22FFL so taping these out should be rather cheap. So the question we should probably be asking is how many base tilese are there and what are they being used for?

 

[ashFTW]

Each new combination needs a new base tile. This should be relatively easy to do - it's produced on 22FFL so taping these out should be rather cheap. So the question we should probably be asking is how many base tilese are there and what are they being used for?

That’s not true when using Foveros Omni. The top tiles can expand beyond the base tile; the logic to connect the tiles needs to be constrained to the overlapping regions of the tiles.

Page 643 - Discussion - Intel current and future Lakes & Rapids thread

Page 643 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

 

[Exist50]

That’s not true when using Foveros Omni

MTL does not use Foveros Omni.

 

[ashFTW]

MTL does not use Foveros Omni.

And what makes you think that?

 

[Exist50]

And what makes you think that?

They've already confirmed it uses 36 micron Foveros, and you can see from everything they've presented that it's not Omni. Believing anything else at this point is pure hopium.

 

[burninatortech4]

Raichu was right:

https://twitter.com/x/status/1561752492052197378

What is ULV core?

 

[ashFTW]

They've already confirmed it uses 36 micron Foveros, and you can see from everything they've presented that it's not Omni. Believing anything else at this point is pure hopium.

Omni may appear with Arrow lake, it’s the logical thing to do with varying sizes of top die.

 

[Exist50]

Omni may appear with Arrow lake, it’s the logical thing to do with varying sizes of top die.

Arrow Lake uses the same Foveros as Meteor Lake.

 

[IntelUser2000]

And what makes you think that?

Did we not discuss this before with you? Meteorlake is basically a "shrink" of Foveros to 36um. Omni is later. Also, teaser for tomorrow's Hot Chips presentation is out already. Nothing about Omni with Arrowlake.

@Exist50 definitely has good info. So I now take his word for it. Like the part about which tiles fit to what functionality, different configurations, he got all of them right.

What is ULV core?

It's an Atom-based core section dedicated to offloading to lower CPU utilization and increase battery life.

 

[ashFTW]

Also, teaser for tomorrow's Hot Chips presentation is out already. Nothing about Omni with Arrowlake.

I’m attending the HC34 conference and looking forward to more details later today.

 

[moinmoin]

What is ULV core?

Ultra low voltage core. In the past that was a way to refer to the U series chips. Though in this case it may refer to a (new?) core in the SoC used as the system controller.