Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Ghostsonplanets]

Without MoP, is Intel gonna be able to tame the RAM latency for PTL-U? That's how they ruined MTL-U and MTL-H.

Latency on MTL/ARL is mainly due to IOSF and Memory Controller being on the SoC.

Panther Lake will solve this by having SoC and Compute Tile being one unified tile.

MOP has advantages, but it's a big cost adder.

 

[Tigerick]

Latency on MTL/ARL is mainly due to IOSF and Memory Controller being on the SoC.

Panther Lake will solve this by having SoC and Compute Tile being one unified tile.

MOP has advantages, but it's a big cost adder.

Yep, Intel maybe late to join the fight but they won't miss:

STX 4+8 HT 16CU vs PTL-H 4+8+4 noHT 12 XE

KRK 4+4 8CU vs PTL-U 4+4 4 XE

 

[dullard]

Now that Intel's feature size is basically meaningless...

Intel has said that they'll use a new node name any time the performance per watt is improved by ~14% or more. So, basically any time a gain is large enough to be noticed by the typical user (most users don't notice something like a 3% gain unless they are timing it with a stopwatch or benchmark software). This could come from optimizations, feature size shrinks, added features, different packaging, or whatever.

 

[Ghostsonplanets]

Yep, Intel maybe late to join the fight but they won't miss:

STX 4+8 HT vs PTL-H 4+8+4 noHT 12 XE

KRK 4+4 vs PTL-U 4+4 4 XE

If PTL can come fast enough in 2025, not everything is lost for Intel next year. If they leave it to ramp for volume at CES 26, outlook will be grim.

Given how much loose lips Intel has been with PTL, hopefully they're considering the former cadence.

 

[igor_kavinski]

I think they are pretty confident about PTL. It should be a decent product. At least nothing as awful as MTL.

 

[Abwx]

Yep, Intel maybe late to join the fight but they won't miss:

STX 4+8 SMT vs PTL-H 4+8+4 noHT 12 XE

Fixed for you, and in this comparison PTL wont stand a chance even if STX was to use Zen 4 cores, a 4 + 8+ 4 configuration is the equivalent of 10P, and only if the 4 P cores have HT, otherwise it s akin to a 9P.

KRK 4+4 vs PTL-U 4+4 4 XE

This one is more balanced since 4 + 4 + 4 can eventualy be comparable to 8P, but same as previously, if there s no HT then that s more of a 7P.

The end result will be dependant of the CPUs IPCs, and also of the process, if it s anything like MTL then it doesnt bode well for Intel.

 

[igor_kavinski]

if it s anything like MTL then it doesnt bode well for Intel.

MTL is a beta CPU. Intel is lucky that they can test their theories and beta hardware products on the general public without any serious backlash.

AMD almost died when they tried the exact same approach with Bulldozer.

 

[Hulk]

Regarding Raptor Lake crashing in games. There is some nuance here.

Intel has specified the 14900K and KS especially at the extreme limit of their performance. What I mean is that if you don't have excellent cooling, power delivery, and the know how to set up load lines and such correctly these parts will run reliably at high frequencies but only under low compute loads. Stress them heavily and they will crash.

Furthermore it takes what I consider crazy voltage, 1.4+ to run 6GHz or higher. So if you are trying to run 1 or 2 cores at really high frequencies now and then you are cooking your CPU for a couple hundred MHz out of 1 or 2 cores now and then. Hello degradation.

Also as I have noted HT also causes problems with stability if you aren't properly set up, powered, cooled...

Want to run nC at 5.5GHz, it's really not a problem with a good mobo, power supply, and cooler. Intel specs these CPU's higher, people "go for it" without the proper experience, and they fail.

Intel could simply down spec the CPU's, which is basically what they have done by releasing new BIOS recommendations.

The better solution of course would be for a more rigorous specification out of the box. Indicate what cooling, motherboard, and applications were used to achieve the numbers indicated on the box. Give us an indication of not how fast the CPU can run but how stably it can run at that frequency.

Of course all of this was the result of Intel needing to compete with AMD at any cost.

 

[dullard]

MTL is a beta CPU. Intel is lucky that they can test their theories and beta hardware products on the general public without any serious backlash.

AMD almost died when they tried the exact same approach with Bulldozer.

Meteor Lake at least performs okay. Nothing stellar, but nothing really off-putting either. So it can work as a beta CPU. Plus, it actually fulfills a need of Intel: getting Intel's CPU-based NPUs into developer's hands. As of earlier this week, over 500 AI models now work on it. That wouldn't have happened without CPUs in the developer's hands. AI would have stayed in the GPU realm for a lot longer.

 

[igor_kavinski]

Of course all of this was the result of Intel needing to compete with AMD at any cost.

Except the cost is that they cheated by disregarding all safety precautions (and probably shutting up a few insiders who warned them against it) and now their cheating has been exposed.

You don't need anything special with Zen 4. If it doesn't have proper cooling, it will throttle and prevent itself from running at frequencies and temperatures that could degrade it within the warranty period.

Intel 7 was tweaked to let 14th gen run at the highest frequencies possible. That tweak was possibly reckless and they most likely knew it. At least one person or a small group of engineers knew it but went ahead anyway because that's what Pat ordered. Must not lose face in public. Must compete with AMD instead of ceding to them. Must show few benchmarks where Raptor Lake is ahead.

Pat was too chicken to be honest. He's afraid of getting sacked by the board. Everything Intel has done so far reeks of desperation. It will only get worse with Zen 5 launch and Arrow Lake.

 

[repoman27]

Let's see:

1. ARL-U's tCPU
2. Sierra Forest
3. Granite Rapids
4. PTL's 4Xe tGPU
5. Upcoming NV ARM SoC

Yep, IF will keep expanding IP of Intel 3 process. It's going to be long term process for IF.

Have the Arrow Lake-U CPU tile and Panther Lake GPU tile been mentioned publicly, or is that just stuff you know / have shared here? I mean it's good that there are some internal client designs on Intel 3 (assuming those are Intel 3 and not Intel 4), but those are both pretty tiny chips, so probably only a few weeks of wafer starts for either one.

 

[AMDK11]

Further thoughts on LionCove:

Taking into account that GoldenCove has 3x FP-ALU + 2x ALU, switching to 4x FPU + 6x ALU in LionCove gives 2x more execution ports, i.e. a +100% increase.

I suspect that this is the most significant change in LionCove compared to previous microarchitectures.

Don't ask how much this will translate into an increase in IPC because honestly I have no idea.

 

[dullard]

Have the Arrow Lake-U CPU tile and Panther Lake GPU tile been mentioned publicly, or is that just stuff you know / have shared here? I mean it's good that there are some internal client designs on Intel 3 (assuming those are Intel 3 and not Intel 4), but those are both pretty tiny chips, so probably only a few weeks of wafer starts for either one.

Look at the very first image at the top of this page.

 

[ondma]

Meteor Lake at least performs okay. Nothing stellar, but nothing really off-putting either. So it can work as a beta CPU. Plus, it actually fulfills a need of Intel: getting Intel's CPU-based NPUs into developer's hands. As of earlier this week, over 500 AI models now work on it. That wouldn't have happened without CPUs in the developer's hands. AI would have stayed in the GPU realm for a lot longer.

Yea, I was just going to comment on this. Meteor Lake may disappoint, but it is far from Bulldozer levels of fail.

 

[Ghostsonplanets]

This one is more balanced since 4 + 4 + 4 can eventualy be comparable to 8P, but same as previously, if there s no HT then that s more of a 7P.

4P + 4LPE. The final 4 are meant to represent the 4 Xe³ cores. 4P+0E+4LPE+4Xe³ Cores.

Have the Arrow Lake-U CPU tile and Panther Lake GPU tile been mentioned publicly, or is that just stuff you know / have shared here? I mean it's good that there are some internal client designs on Intel 3 (assuming those are Intel 3 and not Intel 4), but those are both pretty tiny chips, so probably only a few weeks of wafer starts for either one.

Both are public information*, yes.

*By reliable Intel leakers

 

[Kepler_L2]

Latency on MTL/ARL is mainly due to IOSF and Memory Controller being on the SoC.

Panther Lake will solve this by having SoC and Compute Tile being one unified tile.

MOP has advantages, but it's a big cost adder.

No the problem is just IOSF. Monolithic products like Jasper Lake also have horrible memory latency.

 

[adroc_thurston]

Monolithic products like Jasper Lake also have horrible memory latency.

Dog memory perf on Intel NOCs dates all the way back to Medfield.

 

[AMDK11]

It appears that LionCove is part of the "Royal Core" project.

I have a strange feeling that LionCove "might" bring a greater increase in IPC than is commonly believed.

 

[adroc_thurston]

It appears that LionCove is part of the "Royal Core" project.

There's no magic.

I have a strange feeling that LionCove "might" bring a greater increase in IPC than is commonly believed.

"it came to me in the dream".
Amazing.
(it's low-mid teens IPC, that's it. 12Q for that yea. enjoy!)

 

[H433x0n]

It appears that LionCove is part of the "Royal Core" project.

I have a strange feeling that LionCove "might" bring a greater increase in IPC than is commonly believed.

It's not. These CPUs are in the wild, it's not going to be some out of ordinary increase that's >20% IPC. Even if it did somehow exceed targets and hit +20% IPC, there's inherent issues that will kneecap it. The only surprise (IMO) is how well they got ARL to clock.

 

[AMDK11]

What kind of magic did you expect?

From the very beginning, Intel has used a unified schedule and shares the FPU execution ports with the ALU.

The LionCove project breaks this tradition and relies on separate schedules and execution ports for FPU and a separate one for ALU.

I think this is a big enough change in approach. It would be an even bigger surprise if it turned out that a separate part for the FPU is FP-ALU.

Also, has anyone tested Arrowlake samples at a rigid clock speed and reported the results?

Arrowlake samples are out there and there are no IPC leaks. It's interesting that so far all we have are these Intel forecasts.

 

[adroc_thurston]

From the very beginning, Intel has used a unified schedule and shares the FPU execution ports with the ALU.

The LionCove project breaks this tradition and relies on separate schedules and execution ports for FPU and a separate one for ALU.

I think this is a big enough change in approach. It would be an even bigger surprise if it turned out that a separate part for the FPU is FP-ALU.

There's a lot more to core design than that.
Either way, 12Q for low teens IPC.
Blergh.

 

[AMDK11]

Oh wow. It's good that you made me realize that the core is not only the schedule and execution units. Better late than never.

I only provided one component. Still not enough data on many points of micro architecture.

Including 24 points and it is not certain how many are for the decoder and how many for the UOP cache.

 

[adroc_thurston]

Including 24 points and it is not certain how many are for the decoder and how many for the UOP cache.

the what.
decoding and uop caches are unrelated to scheduler slots/reservation stations.

 

[AMDK11]

the what.
decoding and uop caches are unrelated to scheduler slots/reservation stations.

And where did I write that I said so?