~150 MTr/mm2 is completely wrong (as discussed with witeken). Problem is he doesn't understand. His estimate is way off!
TSMC N3 HP density is 124 MTr/mm2. Intel 3 HP density is 135.74 MTr/mm2. Intel 3 HP density is higher than TSMC N3 by 10%.
And when it comes to HD, TSMC N3 is around 200 MTr/mm2.
So, basically what you are trying to say is:
When TSMC N3 HP is only 124, its HD is ~200.
And when Intel 3 HP is already 136, its HD is only a meager 150???
Your math is wrong.
Intel 4 is 0.6 x 4/ (150 x 240) + 0.4 x 32/ (950 x 240) = ~122.8 MTr, Intel 3 is 0.6 x 4/ (150 x 210) + 0.4 x 32/(950 x 210) = ~140.35
Math looks like it checks out? Witeken said 150, maybe I missed a scaling factor, idk.
So why does TSMC scale so much better than Intel from HP to HD?
TSMC N3 this time around is using finflex- and that's where the HD figure of ~215MTr/mm2 comes from (with the 48nm CGP as well IIRC). The 2-1 variant. The HP cells, however, is still being compared to the 3-3 variants, and that's with the relaxed 54nm CPP figure as well.
TSMC N3 HD vs HP ratio this time around is ~1.73. TSMC N5 HD vs HP was 1.48. That is a significant difference.
Ok, so what's wrong using the 1.5x scaling figure for Intel then that N5 enjoys?
Well, the cell height scaling is quite simply worse. TSMC N5 HD cell height is 210nm, which is the exact same as the cell height of Intel 3 HD.
TSMC's HP cell height is quite high on the other hand, is:
(angstronomics 5nm article)
So what makes Intel 4 HP so dense?
Intel 4's Cell Height is quite low.
If you look at this, you see that Intel 4 CPP isn't anything that amazing. It's between N5 and N3, an closer to N5 to boot. However its height is literally lower than even N3, and by a decent amount too.
So why doesn't Intel 3 cell height scale better when lowering the fin count?
Well, who knows. Maybe the track count just can't scale much lower, since Intel 4's HP metal track count is already impressively low (at 5.33 vs 9 for N3 and N5).
Maybe N5's fin pitch is larger than Intel 4's, which provides it better scaling as you remove fins. Idk.
Regardless, the numbers are right there. Intel themselves claimed a cell height of 210nm for their HD libs, and N5 HD lib cell height is also 210nm. The only thing that's making Intel 4 denser now is the slightly lower CGP of 51 vs 50nm. And for Mark Bohr's calculation, those 2 numbers are pretty much all that matter *** with some asterisks that are described in angstranomics article.
The only thing that can "save" Intel 3's density now is the shrinking of CGP even lower, which wouldn't be
new from Intel (Intel 7 had 60/54 nm CGP variants IIRC) but seeing how it's not listed in the abstract while all the other major points are, I doubt it.
As far as I understand the jump from Intel 4/3 to Intel 20/18A is less about any density increase and more about decreasing cost, increasing yield and significantly higher volume. Intel 4/3 are the last nodes in an unsustainable development of internal first/only nodes whereas Intel 20/18A are the first ones that should make IF actually competitive in the market.
TBH I was also expecting a shrink so it would be more competitive against N3, but who knows ¯\_(ツ)_/¯
I'm always pretty much optimistic for Intel... for the first couple months of the rumor mill
Like shown in the video (and discussed in the other thread), I too remember reading that FinFlex is actually a part of N3B itself. So, N3E is definitely going to have some slight regression after all.
N3E has finflex
They might be what they mean in their slide that Mobile optimization only happens on 18A-P and 14A. They continue their transistor drive current leadership at the cost of density, and low power performance.
Based on that rumor of Intel 18A "high density" cells only being marginally more dense than N5 HD cells, I wonder if that's actually due to them not shrinking cell height/cpp or them just not offering a lower amount of fins until something like 18A-P or 14A. That's my copium at least lol.
But ye I agree, I think intel is laser focused on perf/watt (prob perf/watt specifically for HPC too).
Another interesting find, Just connecting the dots...
Don Soltis (Senior principal engineer and chief architect for Xeon Efficient-core) said last year that Sierra Forest (Intel 3) has 100 billion transistors (approx).
Wild_C on twitter said last year that Sierra Forest (144) has a die area of 578 mm2 (approx).
With this we can directly calculate Sierra Forest on Intel 3 HD cell density at 173 MTr/mm2 (approx).
(Note: 100B transistors has to be 144 and cannot be 288, cos with 288, we arrive at 86.5 which is way below Intel 3 HP cell density itself which is totally wrong. So, 100B has to be 144 only.)
This puts Intel 3 HD (theoretical) peak density at least at 180 MTr/mm2 (approx).
Another key observation is:
HP:HD cell ratio for Intel 14 is 1:1.53, Intel 7 is 1:1.5, TSMC N7 is 1:1.4, N5 is 1:1.48, N3 is around 1.59 i think. The industry average is around 1:1.5. If we apply this to Intel 3, we arrive at ~200 MTr/mm2 (approx). Even assuming worst case and adjusting the ratio to paltry 1.3 for bigger than expected HD cell height, it'll still be ~175 MTr/mm2, which tracks well with Don Soltis+Wild_C numbers.
This puts Intel 3 very near TSMC N3.
SRF is built on both Intel 3 and Intel 7. Without the breakdown of the transistors in the IO vs Compute tiles, the total transistor count figure isn't that helpful for determining the density of Intel 3 itself.
100B transistors has to be 288, cos with 288, we arrive at 86.5, which makes sense. The real density of these server chips should be way below their theoretical density.
Looking at the real density of small mobile chips and seeing how they lineup against server chips is not the play. It's not the area that's the problem, but the completely different ratios of cores/cache/io, and also the iGPU, which is typically made of pretty dense logic (which can provide a decent boost in numbers).
I'm guessing you saw this chart and decided to try this:
We can go ahead and look at an example of this not working for server chips. SPR, on Intel 7, has a density of ~30 Mtr/mm2. What's Intel 7's UHP lib density? ~60MTr/mm2. The ratio there is like 50%. But what if we apply this to GNR since the server to logic density ratio looks to be 1/2? This would mean Intel 3 (using the 288C SRF model) could be estimated to be ~170 MTr.... wait a second....
checks twitter
are you literally not counting the IO tile area... at all? Wth!
So lets pretend that Intel 3 vs Intel 7 IO scaling is 2x. I doubt it's that high, but whatever. Let's cut the area of the IO tiles in half now, add in the 2 compute tiles, an area of ~1397 mm2, 100 billion transistors, gives u a density of ~72, which is roughly half of Intel 3's HD lib density of ~140.
Except all this math is bad, because it's never this simple, and we made way too many assumptions on the way. EMR has a transistor density of ~40 MTr. Does this mean Intel's 7 UHP lib density increased to ~80 MTr/mm2? What about ICL server, with its horrendous transistor density? Mixing in compute and IO tiles too, or just ignoring the IO tiles completely....
I think this exercise was a bit pointless tbh. Way too many assumptions.
Lastly, Intel themselves claim they will have worse transistor density with Intel 3 than TSMC 3nm.
If it was just slightly worse, as you are suggesting, then they almost certainly would have done a " - ~" rather than a "-" since they also used "+~" elsewhere. I think that minus over there is doing a
lot of heavy lifting. And tbh, I would not be surprised if this is specifically in reference to HP logic cells, and ignoring HD cells, SRAM density, analog, etc etc. I also think it's possible the signs for Intel 14A is a lot more wholistic though, since it also includes "mobile" in the target segment. We will see in a couple months ig.