Discussion RISC V Latest Developments Discussion [No Politics]

[DisEnchantment]

Some background on my experience with RISC V...
Five years ago, we were developing a CI/CD pipeline for arm64 SoC in some cloud and we add tests to execute the binaries in there as well.
We actually used some real HW instances using an ARM server chip of that era, unfortunately the vendor quickly dumped us, exited the market and leaving us with some amount of frustration.
We shifted work to Qemu which turns out to be as good as the actual chips themselves, but the emulation is buggy and slow and in the end we end up with qemu-user-static docker images which work quite well for us. We were running arm64 ubuntu cloud images of the time before moving on to docker multi arch qemu images.

Lately, we were approached by many vendors now with upcoming RISC-V chips and out of curiosity I revisited the topic above.
To my pleasant surprise, running RISC-V Qemu is smooth as butter. Emulation is fast, and images from Debian, Ubuntu, Fedora are available out of the box.
I was running ubuntu cloud images problem free. Granted it was headless but I guess with the likes of Imagination Tech offering up their IP for integration, it is only a matter of time.

What is even more interesting is that Yocto/Open Embedded already have a meta layer for RISC-V and apparently T Head already got the kernel packages and manifest for Android 10 working with RISC-V.
Very very impressive for a CPU in such a short span of time. What's more, I see active LLVM, GCC and Kernel development happening.

From latest conferences I saw this slide, I can't help but think that it looks like they are eating somebody's lunch starting from MCUs and moving to Application Processors.


And based on many developments around the world, this trend seems to be accelerating greatly.
Many high profile national and multi national (e.g. EU's EPI ) projects with RISC V are popping up left and right.
Intel is now a premium member of the consortium, with the likes of Google, Alibaba, Huawei etc..
NVDA and soon AMD seems to be doing RISC-V in their GPUs. Xilinx, Infineon, Siemens, Microchip, ST, AD, Renesas etc., already having products in the pipe or already launched.
It will be a matter of time before all these companies start replacing their proprietary Arch with something from RISC V. Tools support, compiler, debugger, OS etc., are taken care by the community.
Interesting as well is that there are lots of performant implementation of RISC V in github as well, XuanTie C910 from T Head/Alibaba, SWerV from WD, and many more.
Embedded Industry already replaced a ton of traditional MCUs with RISC V ones. AI tailored CPUs from Tenstorrent's Jim Keller also seems to be in the spotlight.

Most importantly a bunch of specs got ratified end of last year, mainly accelerated by developments around the world. Interesting times.

 

[DisEnchantment]

It's highly unlikely that RISC-V outright replaces all of it. Even if it did uproot ARM the open nature all but ensures that we get a similar problem all over again. In reality RISC-V just gets added to the end of your existing list.

It is one thing to debate about it in the forums, it is another thing when you develop products that use components from multiple vendors and each one needs a separate tool chain.
How many compilers, do you need for one product, how many debuggers. World is bigger than PC and mobile phones, how many MCUs in one satellite, or a plane or vehicle or a fridge are there?
How many compilers do you pay for, Altium, Windriver, GreenHills, Keil... how many OS, Integrity, QNX, FreeRTOS, it is very tiring.
Having one compiler clang or gcc to compile for everything is something your FAE at Renesas or Infineon would be dying to provide. Or even better, nothing to provide, everything is upstream

 

[Mopetar]

I think you're making a rather large assumption that things will just work out in the best-case scenario that you've envisioned. Eventually some vendor will get the bright idea that they can offer a better product if they make some customization to the ISA and release some of their own tools to support their custom hardware. All of them will try to do this because the ones that can't live in a very cut throat market and have no leverage.

 

[moinmoin]

I'll put it another way: Linux is a mess, highly fragmented with a lot of competing projects and ecosystems on different layers. But it still managed to become the primary focus for any effort where having an open source operation system is a requirement. Risc-V has the chance to achieve the same for open source CPUs.

 

[DisEnchantment]

I think you're making a rather large assumption that things will just work out in the best-case scenario that you've envisioned. Eventually some vendor will get the bright idea that they can offer a better product if they make some customization to the ISA and release some of their own tools to support their custom hardware. All of them will try to do this because the ones that can't live in a very cut throat market and have no leverage.

Its a professional experience not an assumption.
Do you really think you get cutting edge C++17 support when you buy PIC or AVR MCUs?
All these people are so far behind with some compilers dating to previous century. Check the roots of CA850.
Try buying HW Debuggers next.
Having an ISA with support from latest and greatest GCC and clang means your code can be reuse across lots of MCUs and platforms. Same compiler. Not one off compiler never to be supported again.
This a a real problem which if you face one you would wish you have common or least popular ISA which a lot of vendors support which everyone can use. RISC V support in clang and GCC is thriving due to countless support from multiple companies.
You can even run qemu for RISCV target, which is a dream for many common MCUs.

 

[Thala]

Eventually some vendor will get the bright idea that they can offer a better product if they make some customization to the ISA and release some of their own tools to support their custom hardware. All of them will try to do this because the ones that can't live in a very cut throat market and have no leverage.

Thats what we are doing, we forked the toolchain because we are adding custom extensions to our RISC-V cores. However that is what everyone else doing as well in the microcontroller/embedded space.

 

[desrever]

I'll put it another way: Linux is a mess, highly fragmented with a lot of competing projects and ecosystems on different layers. But it still managed to become the primary focus for any effort where having an open source operation system is a requirement. Risc-V has the chance to achieve the same for open source CPUs.

Linux is an anomaly rather than the rule. Linux is a small part of the much wider Linux ecosystem which developed with very specific circumstances. Originally, the open sourceness of it wasn't the attraction, it was the cost. Linux really got its popularity in servers due to low cost web servers and embedded devices where the cost of windows didn't make sense. I don't know the specifics on cost of using RISC-V vs ARM and it could do the same but I think the economics may not be as favourable.

I think the development of semiconductor engineering will move away from licensing the ISA directly and building your own blocks. Everyone licenses their IPs directly these days, the cost of the ISA when licensing an IP block is probably not significant so it will all come down to performance and support. RISC-V can definitely have a niche on the low end but I don't see it doing much to gain momentum outside of it. MIPS has been around for a long time and never went beyond low end embedded devices, theres not much the RISC-V offers today beyond what MIPS offered 20 years ago IMO.

 

[Doug S]

I'll put it another way: Linux is a mess, highly fragmented with a lot of competing projects and ecosystems on different layers. But it still managed to become the primary focus for any effort where having an open source operation system is a requirement. Risc-V has the chance to achieve the same for open source CPUs.

Linux was able to do so because there wasn't much in the way of cheaply licensable alternatives, there was no "ARM" for embedded software where the cost of the OS became a minor consideration in your BOM. Had there been a dominant embedded OS with the feature set approximating that of Linux you could license for 10 or 20 cents per unit Linux would have had a lot harder time owning the market in devices like wireless routers and satellite DVRs. Linux took that market because of price, not openness. Most of those devices run a generic Linux kernel, with device drivers added as needed for e.g. wifi radios and satellite tuners, which are usually sourced from third parties.

They aren't using the "openness" to tweak it - they want to avoid that as much as possible because that makes it more work to upgrade to a newer version to keep ahead of security issues. They provide a link to the generic Linux kernel, use their third party provided binary only drivers, and their GPL obligation is covered so they don't have to pay a penny. That's why Linux is much more dominant in the embedded market than in the server market, where the price of the OS is a much smaller fraction of the TCO.

Price is the most important "feature" of RISC-V as far as those on razor thin profit margins are concerned, too. That's why it will see most of its success in the low end, and is not going to have even the slightest impact on servers or desktop/laptop - other than maybe Chromebook down the road.

 

[DrMrLordX]

Let's bookmark this thread and come back to it in one to two decades. Hope you all can stick around that long.

I've been here more than two decades (scary). Think the forum can last another 22 years?

 

[moinmoin]

Linux was able to do so because there wasn't much in the way of cheaply licensable alternatives, there was no "ARM" for embedded software where the cost of the OS became a minor consideration in your BOM. Had there been a dominant embedded OS with the feature set approximating that of Linux you could license for 10 or 20 cents per unit Linux would have had a lot harder time owning the market in devices like wireless routers and satellite DVRs. Linux took that market because of price, not openness.

You couldn't be farther off. Linux became the open source focus even though there were even "more free" OSes available in all the BSD variants. And the reason why Linux turned to dominate despite the BSD alternatives, while in this exact way fostering an open source ecosystem with participants from all possible areas, can show you what's possible with Risc-V that's not with all other major ISAs.

Linux is an anomaly rather than the rule. Linux is a small part of the much wider Linux ecosystem which developed with very specific circumstances. Originally, the open sourceness of it wasn't the attraction, it was the cost. Linux really got its popularity in servers due to low cost web servers and embedded devices where the cost of windows didn't make sense.

Strongly disagree. Maybe you are too young, but cost doesn't even enter the picture if the OS has bad support, be it software or hardware. Linux's first breakthrough wasn't being cheaper than other solutions but being popular enough that in cases where it could be considered cheap it already included the necessary hardware support through voluntary contributors that already worked on it. And that initial software and hardware support only happened because it's open source. More specifically (and contrary to all the BSD variants) it's open source that rewards voluntary contributors by always keeping the source open (in contrast to efforts for BSD variants where any development can be turned closed source again) which is what fostered the whole open source ecosystem. Commercial players that purely looked at the cost joined only later (and reluctantly, IBM's involvement was a sensation, Balmer called the whole open source ecosystem a cancer back then).

MIPS has been around for a long time and never went beyond low end embedded devices

As said before MIPS also uses a proprietary license. That excludes any kind of dedicated open source ecosystem from the very beginning.

I've been here more than two decades (scary). Think the forum can last another 22 years?

I'm kinda afraid that the forum outlasts the site it's for.

 

[Doug S]

You couldn't be farther off. Linux became the open source focus even though there were even "more free" OSes available in all the BSD variants. And the reason why Linux turned to dominate despite the BSD alternatives, while in this exact way fostering an open source ecosystem with participants from all possible areas, can show you what's possible with Risc-V that's not with all other major ISAs.

You don't explain why you think Linux beat the BSDs despite being "less free" in a licensing sense.

Cost wise Linux and BSD are equally free, and cost is the reason why Linux succeeded where it did and failed where it did. If it was about licensing freedom, BSD would have won.

 

[Thala]

And the reason why Linux turned to dominate despite the BSD alternatives, while in this exact way fostering an open source ecosystem with participants from all possible areas, can show you what's possible with Risc-V that's not with all other major ISAs.

The problem you neglect is, that the major difference between Linux and RISC-V is, that in case of RISC-V only the ISA is free but not necessarily the implementations. In case of Linux the interfaces AND the implementation is free. As example, SiFive is not openly disclosing the implementations but they are asking for license fees - there is nothing free about the SiFive RISC-V cores. In contrast the Linux implementation is open and free.

 

[moinmoin]

You don't explain why you think Linux beat the BSDs despite being "less free" in a licensing sense.

Cost wise Linux and BSD are equally free, and cost is the reason why Linux succeeded where it did and failed where it did. If it was about licensing freedom, BSD would have won.

I clumsily tried to. It is the "less free" libre licensing terms that ensures the whole ecosystem around Linux couldn't be locked out suddenly. Linux got to where it is now not through corporate and commercial support but through voluntary contributors. And that made the difference. The different BSD variants on the other hand have way smaller communities and rely much more on corporate support by a few companies that in turn rely on the ability of closing the sources again (to include proprietary IPs or whatever).

The problem you neglect is, that the major difference between Linux and RISC-V is, that in case of RISC-V only the ISA is free but not necessarily the implementations. In case of Linux the interfaces AND the implementation is free. As example, SiFive is not openly disclosing the implementations but they are asking for license fees - there is nothing free about the SiFive RISC-V cores. In contrast the Linux implementation is open and free.

That's indeed an issue I see as well, especially that while there are plenty of open source implementations, the lack of libre licenses may lead to overall less continued open development on them. That would be unfortunate since there are quite some implementations to work with.

Open source implementations of Risc-V CPUs I'm aware of:

GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation

A FPGA friendly 32 bit RISC-V CPU implementation. Contribute to SpinalHDL/VexRiscv development by creating an account on GitHub.

github.com

GitHub - stnolting/neorv32: :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. - stnolting/neorv32

github.com

GitHub - riscv-boom/riscv-boom: SonicBOOM: The Berkeley Out-of-Order Machine

SonicBOOM: The Berkeley Out-of-Order Machine. Contribute to riscv-boom/riscv-boom development by creating an account on GitHub.

github.com

GitHub - chipsalliance/Cores-VeeR-EH1: VeeR EH1 core

VeeR EH1 core. Contribute to chipsalliance/Cores-VeeR-EH1 development by creating an account on GitHub.

github.com

GitHub - bluespec/Piccolo: RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT) - bluespec/Piccolo

github.com

GitHub - bluespec/Flute: RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance - bluespec/Flute

github.com

GitHub - bluespec/Toooba: RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT - bluespec/Toooba

github.com

GitHub - openhwgroup/cva5: The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations. - openhwgroup/cva5

github.com

 

[Zor Prime]

Not sure what you are talking about. You can build and run ARM64 builds of Haiku OS right now, while on RISC-V only parts of the bootloader works. You are right, the ARM64 build still has lots of issues but its far more advanced than the RISC-V build.

My bad, it was my understanding Haiku OS was getting to desktop on RISC-V. I must have been looking at screenshots of something else then.

edit: Guess it wasn't my bad. RISC-V port did hit the finish line before ARM as evidenced here, almost a year ago.

 

[DisEnchantment]

Linux became the open source focus even though there were even "more free" OSes available in all the BSD variants. And the reason why Linux turned to dominate despite the BSD alternatives, while in this exact way fostering an open source ecosystem with participants from all possible areas, can show you what's possible with Risc-V that's not with all other major ISAs.

VxWorks, QNX and Integrity dominate mission critical systems. Then theres AUTOSAR, OSEK, FreeRTOS, Micrium, and countless proprietary ones
Not surprising but the vast billions of MCUs don't run Linux

VxWorks, Integrity added RISC-V support for a while now.

Open source implementations of Risc-V CPUs I'm aware of:

GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation

A FPGA friendly 32 bit RISC-V CPU implementation. Contribute to SpinalHDL/VexRiscv development by creating an account on GitHub.

github.com

Missed one important one

GitHub - T-head-Semi/openc910: OpenXuantie - OpenC910 Core

OpenXuantie - OpenC910 Core. Contribute to T-head-Semi/openc910 development by creating an account on GitHub.

github.com

C910 from Alibaba.

As said before MIPS also uses a proprietary license. That excludes any kind of dedicated open source ecosystem from the very beginning.

Looking at RISC-V Consortium members you can tell the ISA has lots of interest which MIPS could never have garnered.
Excluding Arm every design house is there.

 

[nicalandia]

Impressive Specs for this CPU

Veyron V1 Highlights

• Eight wide, aggressive out-of-order pipeline
• 3.6GHz
• 5nm process technology
• 16 cores per cluster
• High core count multi-cluster scalability (up to 192 cores)
• 48MB of shared L3 cache
• Advanced side channel attack mitigations
• Comprehensive RAS features
• System-level code profiling
• Provided with IOMMU and Advanced Interrupt Architecture (AIA) system IP
• SDK released with the necessary software already ported to Veyron
• Veyron V1 Development Platform available

Ventana Micro Systems Veyron V1 RISC-V Processors Launched

Ventana Micro Systems Inc has made an announcement about their new family of high-performance processors the Veyron V1.

www.storagereview.com

 

[DrMrLordX]

Impressive Specs for this CPU

Actually, yes, yes indeed. Hmm wonder how much that's gonna cost to get a system in the desktop chassis?

 

[DrMrLordX]

@Henry swagger

There something you want to say?

 

[soresu]

Actually, yes, yes indeed. Hmm wonder how much that's gonna cost to get a system in the desktop chassis?

Lol $5 to make the chip and $50 to license the Veyron name from Bugati 😂🤣

 

[soresu]

I clumsily tried to. It is the "less free" libre licensing terms that ensures the whole ecosystem around Linux couldn't be locked out suddenly. Linux got to where it is now not through corporate and commercial support but through voluntary contributors. And that made the difference. The different BSD variants on the other hand have way smaller communities and rely much more on corporate support by a few companies that in turn rely on the ability of closing the sources again (to include proprietary IPs or whatever).


That's indeed an issue I see as well, especially that while there are plenty of open source implementations, the lack of libre licenses may lead to overall less continued open development on them. That would be unfortunate since there are quite some implementations to work with.

Open source implementations of Risc-V CPUs I'm aware of:

GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation

A FPGA friendly 32 bit RISC-V CPU implementation. Contribute to SpinalHDL/VexRiscv development by creating an account on GitHub.

github.com

GitHub - stnolting/neorv32: :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. - stnolting/neorv32

github.com

GitHub - riscv-boom/riscv-boom: SonicBOOM: The Berkeley Out-of-Order Machine

SonicBOOM: The Berkeley Out-of-Order Machine. Contribute to riscv-boom/riscv-boom development by creating an account on GitHub.

github.com

GitHub - chipsalliance/Cores-VeeR-EH1: VeeR EH1 core

VeeR EH1 core. Contribute to chipsalliance/Cores-VeeR-EH1 development by creating an account on GitHub.

github.com

GitHub - bluespec/Piccolo: RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT) - bluespec/Piccolo

github.com

GitHub - bluespec/Flute: RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance - bluespec/Flute

github.com

GitHub - bluespec/Toooba: RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT - bluespec/Toooba

github.com

GitHub - openhwgroup/cva5: The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations. - openhwgroup/cva5

github.com

Not sure if you know about IIT Madras's RISC-V design project called SHAKTI but at least 2 cores have already been completed.

There is another program in India too called DIR-V which announced a Vega CPU some time ago.

 

[nicalandia]

WCCFTECH Just Posted the article.

RISC-V Architecture To Tackle AMD & Intel x86 Chips With 192 Cores Built on 5nm Process Node

Ventana Microsystems Veyron V1 RISC-V chip is looking to take this startup's new server based chip into the marketplace with AMD and Intel.

wccftech.com

 

[Ajay]

WCCFTECH Just Posted the article.

RISC-V Architecture To Tackle AMD & Intel x86 Chips With 192 Cores Built on 5nm Process Node

Ventana Microsystems Veyron V1 RISC-V chip is looking to take this startup's new server based chip into the marketplace with AMD and Intel.

wccftech.com

I don't really like headlines like this. x86-64 is so dominate (in servers) that I think the title for these sorts of things should be "Plans to make inroads into the datacenter/cloud provider markets" - or the like.

Yes, it's a nit pick.

 

[eek2121]

I have a RISC-V based SBC coming some time this month. It is almost as fast as the Pi 4 from a CPU performance standpoint and faster from a GPU standpoint. It also has native Linux kernel support being merged soon (if not already), and Ubuntu support as well.

RISC-V IMO is far more interesting than ARM or x86.

 

[nicalandia]

I have a RISC-V based SBC coming some time this month. It is almost as fast as the Pi 4 from a CPU performance standpoint and faster from a GPU standpoint. It also has native Linux kernel support being merged soon (if not already), and Ubuntu support as well.

RISC-V IMO is far more interesting than ARM or x86.

RISC-V is indeed more interesting than ARM and x86 and I would say more important than any of those for the future of computing(at least from a ideological standpoint of making OpenSource Hardware and Software that will help humanity in the future). I hope RISC-V Succeeds.

 

[DrMrLordX]

Lol $5 to make the chip and $50 to license the Veyron name from Bugati 😂🤣

Yarr too true. Sadly it's listed as a developer platform and those tend to be $$$. Plus yes the extra $50 on top because hey it's a Bugatti.

 

[moinmoin]

Not sure if you know about IIT Madras's RISC-V design project called SHAKTI but at least 2 cores have already been completed.

There is another program in India too called DIR-V which announced a Vega CPU some time ago.

No I didn't, thanks for mentioning these!

Shakti Processor | Home

shakti.org.in

cores · GitLab

This groups contains the source-code for all the processors built under the SHAKTI program

gitlab.com

https://vegaprocessors.in/

Vega doesn't appear to be open source though?