Discussion RISC V Latest Developments Discussion [No Politics]

[DisEnchantment]

Some background on my experience with RISC V...
Five years ago, we were developing a CI/CD pipeline for arm64 SoC in some cloud and we add tests to execute the binaries in there as well.
We actually used some real HW instances using an ARM server chip of that era, unfortunately the vendor quickly dumped us, exited the market and leaving us with some amount of frustration.
We shifted work to Qemu which turns out to be as good as the actual chips themselves, but the emulation is buggy and slow and in the end we end up with qemu-user-static docker images which work quite well for us. We were running arm64 ubuntu cloud images of the time before moving on to docker multi arch qemu images.

Lately, we were approached by many vendors now with upcoming RISC-V chips and out of curiosity I revisited the topic above.
To my pleasant surprise, running RISC-V Qemu is smooth as butter. Emulation is fast, and images from Debian, Ubuntu, Fedora are available out of the box.
I was running ubuntu cloud images problem free. Granted it was headless but I guess with the likes of Imagination Tech offering up their IP for integration, it is only a matter of time.

What is even more interesting is that Yocto/Open Embedded already have a meta layer for RISC-V and apparently T Head already got the kernel packages and manifest for Android 10 working with RISC-V.
Very very impressive for a CPU in such a short span of time. What's more, I see active LLVM, GCC and Kernel development happening.

From latest conferences I saw this slide, I can't help but think that it looks like they are eating somebody's lunch starting from MCUs and moving to Application Processors.


And based on many developments around the world, this trend seems to be accelerating greatly.
Many high profile national and multi national (e.g. EU's EPI ) projects with RISC V are popping up left and right.
Intel is now a premium member of the consortium, with the likes of Google, Alibaba, Huawei etc..
NVDA and soon AMD seems to be doing RISC-V in their GPUs. Xilinx, Infineon, Siemens, Microchip, ST, AD, Renesas etc., already having products in the pipe or already launched.
It will be a matter of time before all these companies start replacing their proprietary Arch with something from RISC V. Tools support, compiler, debugger, OS etc., are taken care by the community.
Interesting as well is that there are lots of performant implementation of RISC V in github as well, XuanTie C910 from T Head/Alibaba, SWerV from WD, and many more.
Embedded Industry already replaced a ton of traditional MCUs with RISC V ones. AI tailored CPUs from Tenstorrent's Jim Keller also seems to be in the spotlight.

Most importantly a bunch of specs got ratified end of last year, mainly accelerated by developments around the world. Interesting times.

 

[coercitiv]

Re-posting this from the Zen 5 thread. For anyone interested, Tenstorrent had a live event on their RISC-V IP with multiple keynotes today, and they will have one tomorrow as well. The content is available on their YT channel, under streams:

https://www.youtube.com/@tenstorrentinc/streams

 

[Nothingness]

These are impressive results.
I have no time watching the streams. Are these projected results or do they have a chip in their hands with the claimed perf, TDP and frequency?

 

[maddie]

Another drop.

"Finally, although secondary to the video encode capabilities of the MA35D, it’s interesting to note that the management processors in the VPU have shifted from Arm to RISC-V. Whereas the U30’s processors used quad core Cortex-A53 cores, the MA35D VPU uses a pair of quad core RISC-V cores – though AMD doesn’t specify whose. The RISC-V architecture has been quietly pushing out Arm for management controllers such as these, and this is another example of that transition in action."

AMD Announces Alveo MA35D Media Accelerator: AV1 Video Encode at 1W Per Stream​

 

[serpretetsky]

These are impressive results.
I have no time watching the streams. Are these projected results or do they have a chip in their hands with the claimed perf, TDP and frequency?

Its not very clear to me. He says they started benchmarking it (ascalon) and were impressed with the performance. But it's he didn't really explicitly say if these are actual chips or simulations.

timestamped:

 

[Shivansps]

Any news of actually good RISC-V cpus coming in SBC format?

Link!

Microsoft plans major platform upgrades for 'Windows 12' that will modernize the OS with AI, faster updates, and better security

Windows "CorePC" is the spiritual successor to Windows "Core OS."

www.windowscentral.com

This gives me Windows ME PTSD but well see.

 

[igor_kavinski]

Nerds Talking to Nerds About RISC-V hosted by Tenstorrent | RISC-V International

Hybrid Event - This event is hosted by Tenstorrent.

community.riscv.org

For the Jim Keller and Raja Koduri fans.

 

[soresu]

Any news of actually good RISC-V cpus coming in SBC format?


This gives me Windows ME PTSD but well see.

Currently it's a platform problem I think.

No one is making any high end ARM devices like Mac mini but with platform freedom.

The closest thing Is Project Volterra based on 2020 ARM IP - a nice step forward from A76 SBCs, but still nearly 3 full years behind the state of the art and not at all cheap for what it's offering as a WinARM devkit either.

For RISC-V I don't see that level of power landing in modestly priced SBCs without someone like Google putting their own money into it.

 

[Heartbreaker]

Re-posting this from the Zen 5 thread. For anyone interested, Tenstorrent had a live event on their RISC-V IP with multiple keynotes today, and they will have one tomorrow as well. The content is available on their YT channel, under streams:

https://www.youtube.com/@tenstorrentinc/streams

I watched to the first break so far at 1 hour (I think you can really skip the first 28 minutes).

Pretty big news for me that they are doing Risc-V cores at all. Jim Keller seems EXTREMELY bullish on Risc-V. He makes a lot of good points about not being tied up by the Arm license.

Raja Koduri is on Board, as in literally on the companies board, but it sounds he will be hands on, he was in the audience, and Jim joked that about having someone to design them a GPU. He seemed to mention being involved with some stealth startups with Raja. So for all the crap that Raja gets on forums, he seems to have the respect of Jim Keller...

 

[coercitiv]

Raja Koduri is on Board, as in literally on the companies board, but it sounds he will be hands on, he was in the audience, and Jim joked that about having someone to design them a GPU. He seemed to mention being involved with some stealth startups with Raja. So for all the crap that Raja gets on forums, he seems to have the respect of Jim Keller...

Yeah, I saw this pic posted by Keller two days ago but I forgot to mention it.



I'm not sure what to make of all this, including RISC-V as a whole, but I can't shake the fact that I really like the idea of a more open (alternative) ecosystem. Not a fan of Raja, though it seems to me the experience at Intel has changed him for the better: failure is bitter but still good medicine in the right dosage (and I'm not implying it was his failure, usually it's more complicated than that).

 

[Heartbreaker]

Not a fan of Raja, though it seems to me the experience at Intel has changed him for the better: failure is bitter but still good medicine in the right dosage (and I'm not implying it was his failure, usually it's more complicated than that).

Hard to know what really goes on behind the scenes, but outwardly for Raja at AMD/Intel it hasn't been a great look. Big talk and disappointing execution while he was at each company. That Keller respects him enough to bring him on board implies to me, that Raja is more effective than he appears to outsiders.

Also amazing that Jim has a view of what Zen 5 should be like given when he left AMD.

I don't think Jim wants to cross the line into outright disparagement of Intel, but definitely got the sense in his presentation, that his time at AMD was much better for him, than his time at Intel.

 

[Mopetar]

Raja is probably a good engineer (he was at ATI for years prior to their acquisition by AMD) that just isn't good at managing. He wouldn't even be considered for a management position if he didn't have some engineering chops.

It is entirely possible that he's used his failures as a learning experience and will be better as a result. The Steve Jobs that came back and resurrected Apple was quite different from the Steve Jobs that had been ousted from the company roughly a decade prior.

A smaller group is easier to manage and if it lets Raja put his talents to greater effect it may turn out a lot better.

 

[soresu]

Not sure how big the SiFive P870 is based on this Serve The Home article on the HotChips 2023 presentation.

Someone want to fill me in on whether it is 6 wide from the dispath/decode, or 4 wide from the 4 ALUs in the integer part?

 

[JoeRambo]

Someone want to fill me in on whether it is 6 wide from the dispath/decode, or 4 wide from the 4 ALUs in the integer part?

Hot Chips 2023: SiFive’s P870 Takes RISC-V Further

RISC-V is an open instruction set architecture, which means that anyone can create a core that understands RISC-V instructions without worrying about patents and licenses. SiFive is an important pl…

chipsandcheese.com

Will fill You on this and all other details. World class reporting really compared to marketing parrots.

P.S. They also have excellent piece on Ventana's efforts:

Hot Chips 2023: Ventana’s Unconventional Veyron V1

The RISC-V scene has been heating up. SiFive’s designs have moved into higher power and performance envelopes. Alibaba’s T-HEAD division has been creating RISC-V chips in a bid to devel…

chipsandcheese.com

 

[NostaSeronx]

Someone want to fill me in on whether it is 6 wide from the dispath/decode, or 4 wide from the 4 ALUs in the integer part?

It's 5 ALU-wide in the Integer segment.

Rumors from StarFive state that they will have a P870-variant in the JH9100 in 2025.

JH7110 = 4x U74
JH8100 = 2x or 4x P670 and 2x or 4x P470 (there is rumors that for the higher second number (left to right) = JH8200 for 4x/4x and JH8100 for 2x/4x)
JH9100 = 2x P870, 4x P670, 4x P470

 

[Mopetar]

Someone want to fill me in on whether it is 6 wide from the dispath/decode, or 4 wide from the 4 ALUs in the integer part?

Each of the different execution units is counted, so it's a 6-wide design as far as integer operations are concerned. However only 5 of those can be ALU instructions and multiplication and division are more limited.

 

[soresu]

Each of the different execution units is counted, so it's a 6-wide design as far as integer operations are concerned. However only 5 of those can be ALU instructions and multiplication and division are more limited.

A shame it's not going to be around for a while - but at least it shows that RV is only 2-3 years behind at this point if the assertions of Cortex X2 level performance are justified.

 

[Shivansps]

its not much, but the TH1520 of the Lichee is already faster than a RPI4, that makes it faster than most ARM SBCs, except for the RK3588 ones. But the price is terrible.

Too bad about missing OpenGL support, it seems RISC-V is following the example of incluiding terrible drivers and development is focused on android.

 

[eek2121]

its not much, but the TH1520 of the Lichee is already faster than a RPI4, that makes it faster than most ARM SBCs, except for the RK3588 ones. But the price is terrible.

Too bad about missing OpenGL support, it seems RISC-V is following the example of incluiding terrible drivers and development is focused on android.

I have a Lichee Pi 4a. It is a neat little setup. The actual SoC and other components are in a modular DIMM style form factor, so you can replace the board with one that lets you cluster them. They are releasing a board that supports 7 of them very soon. They also have some other products coming.

The board itself is great. Very smooth experience.

Agree about the graphics drivers.

 

[Shivansps]

The price is not attractive for one looking for just a SBC rather than looking to cluster them. But yeah it definatelly looks OK, specially when you consider the ARM SBC industry loves to go back instead of moving forward.

 

[Simon04090]

Hot Chips 2023: SiFive’s P870 Takes RISC-V Further

RISC-V is an open instruction set architecture, which means that anyone can create a core that understands RISC-V instructions without worrying about patents and licenses. SiFive is an important pl…

chipsandcheese.com

Will fill You on this and all other details. World class reporting really compared to marketing parrots.

Apparently I-Fetch from L1I-Cache is 36B/cycle (or 9 uncompressed or 18 compressed instructions or any mixture). How does this fit with a 6-wide decode?

Apart from this, on paper it looks quite impressive, although store and load queues are a bit small.

 

[Mopetar]

Apparently I-Fetch from L1I-Cache is 36B/cycle (or 9 uncompressed or 18 compressed instructions or any mixture). How does this fit with a 6-wide decode?

My best guess is that it's for short branches where if you have some simple switch cases, etc. pulling in up to 17 other instructions means you might have already fetched the next one you need before you realize you need it. If the decoder is well designed for something like that it could theoretically discard fetched instructions that it knows it won't execute and keep the backend better fed.

There could be other reasons as well. Even assuming mostly sequential code, fetching more at once means fewer cache accesses. That could theoretically improve performance or even reduce power use.

 

[eek2121]

The price is not attractive for one looking for just a SBC rather than looking to cluster them. But yeah it definatelly looks OK, specially when you consider the ARM SBC industry loves to go back instead of moving forward.

Depends on what your needs are. I bought one for prototyping a unique idea I am working on. No other SBC quite fit my needs for the price.

 

[soresu]

Too bad about missing OpenGL support

Vulkan support for Zink?

 

[JoeRambo]

Apparently I-Fetch from L1I-Cache is 36B/cycle (or 9 uncompressed or 18 compressed instructions or any mixture). How does this fit with a 6-wide decode?

I have been thinking about it and the least retarded explanation i can come up with is this:

X86 stuff has so called "instruction" predecode, where instruction boundaries and stuff are found, so that decoders are focused on instruction decode. RISC-V has 32bit instructions that are both blessing and curse and the core has to rely on macro fusion to perform.
So while 6 decoders for RISC-V are worth probably 3-4 x64 decoders, if instruction fetch is doing some "work" and marking macro fusion boundaries and then full bundle is fed into decoder that fuses them into uOP for core? Now that would change the equation from "just 6, meh" to "this looks quite powerful, 6 instructions and 3 can be fused, i wonder if they did research of real world code mixtures".

So the jury is still out, but it's clear that RISC-V is no longer targetting shoe box computing and want the ARM pie.

 

[naukkis]

RISC-V has 32bit instructions that are both blessing and curse and the core has to rely on macro fusion to perform.

Risc-V doesn't have fixed length instructions. Instruction length can vary from 16 to 192 bits and more. Risc-v differs from x86 how different length instructions are encoded, Risc-V encoding is aligned to 16 bits and instructions have sane encoding where instruction boundaries can be found easily.