Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[leoneazzurro]

The "cores" are supposed to be around since last year (Genoa samples rumored to be sampling to selected customers, IIRC there were also references in the Financial Keynotes). So probably there was/is some concern about the platform, maybe about the costs of DDR5 modules, maybe not.

 

[poke01]

It's funny how people trust AMD's slides but have huge doubts on Intel's and Nvidia. Like AMD is a saint and does not lie.

is not the goal that AMD aimed for, or the SMT performance with Zen4 is lar

It's either Cinebench ST is not the goal that AMD aimed for, or the SMT performance with Zen4 is larger than expected which would be enough to generate 31% advantage against 12900k in Blender.

View attachment 61942

It says up to 31%. Probably some edge case. So its not even a definite 31% increase in blender over the 12900K

 

[inf64]

Hey, let's not walk back on outrageous claims of some forum members around here:



And so on.

But i think an important point is that Zen4 will still be very awesome CPU, if they can achieve >5Ghz all core 6950x i will be very happy buyer.

Have a little bit of faith Joe. Alder Lake has ~11-12% higher average IPC than Zen3. If AMD hits ~19-20% higher IPC for Zen4 vs Zen3 they are golden.

 

[Thunder 57]

Anyone else notice the lack of overclocking being mentioned for B650? Is that going to be the new A chipset and a way to hide price hikes? Not that I think overclocking is a big deal these days anyway, I'd certainly hate to see them take away a feature.

 

[biostud]

It's funny how people trust AMD's slides but have huge doubts on Intel's and Nvidia. Like AMD is a saint and does not lie.


It says up to 31%. Probably some edge case. So its not even a definite 31% increase in blender over the 12900K

I haven't been following intels recently, but AMD's claims regarding performance the last couple of years has actually been quite accurate. So why would they start changing that?

 

[poke01]

What matters at the end of the day even more than IPC itself is perf/W improvement, because that has the biggest impact on both server and mobile.

We all know Apple will be king in Perf/W as thats always been their goal. If AMD was indeed ahead in that, AMD would have shouted from the rooftops.

 

[Abwx]

It's funny how people trust AMD's slides but have huge doubts on Intel's and Nvidia. Like AMD is a saint and does not lie.


It says up to 31%. Probably some edge case. So its not even a definite 31% increase in blender over the 12900K

First troll of the day who post without even reading the previous posts..

It s not 31%, it s 45% faster than ADL...

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[biostud]

The "cores" are supposed to be around since last year (Genoa samples rumored to be sampling to selected customers, IIRC there were also references in the Financial Keynotes). So probably there was/is some concern about the platform, maybe about the costs of DDR5 modules, maybe not.

Everybody talks about AVX-512 like it is the holy grail, and I've never actually understood if it was important to me as a gamer/photo editor, or who really benefits from having these.

 

[JoeRambo]

If AMD hits ~19-20% higher IPC for Zen4 vs Zen3 they are golden.

Doubt it. They claim "> 15% ST performance uplift" on slides and have 10% higher clocks, so IPC increase is 5-10% max, not really "massive".

 

[Qwertilot]

Eh before you get too disappointed about all clocks and little IPC maybe wait and see what the power curve is like?

What matters at the end of the day even more than IPC itself is perf/W improvement, because that has the biggest impact on both server and mobile.

Well, if they'd really pushed perf/W but not mentioned it then I'll choose to be disappointed on those grounds I also just don't like the way the top few SKU's are having their TDP raised for really quite marginal gains.
(Obviously Intel have been much worse at this recently!).

The integrated iGpu is a very good thing though, the lack of that in Zen3 is why I got a 12600 which will probably do me for a decade or so.

 

[inf64]

Doubt it. They claim "> 15% ST performance uplift" on slides and have 10% higher clocks, so IPC increase is 5-10% max, not really "massive".

They claim that the slowest single-thread performance increase is not lower than 15%. That means that the lowest IPC uplift figure in "some" workload might be as low as 5% as the ST clocks are ~10% higher vs Zen3 .

If you check the intel 's ADL IPC uplift slide, they have an IPC regression in three workloads:


For Zen4, 15% is the minimum ST uplift and I wouldn't be surprised that it happens in R23. Also, note that AMD didn't state at what frequency the "pre-production" (not final) Zen4 16 part ran - we have no idea about the ST clock or MT clocks.

 

[poke01]

First troll of the day who post without even reading the previous posts..

It s not 31%, it s 45% faster than ADL...

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Mate, AMD themselves said up to 31% faster than 12900K.

Anyway this is last gen vs next gen.
wait for 13th gen vs zen4.

 

[exquisitechar]

First troll of the day who post without even reading the previous posts..

It s not 31%, it s 45% faster than ADL...

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That means it did it in 45% less time. It’s 31% faster.

 

[insertcarehere]

They claim that the slowest single-thread performance increase is not lower than 15%. That means that the lowest IPC uplift figure in "some" workload might be as low as 5% as the ST clocks are ~10% higher vs Zen3 .

If you check the intel 's ADL IPC uplift slide, they have an IPC regression in three workloads:
View attachment 61952

For Zen4, 15% is the minimum ST uplift and I wouldn't be surprised that it happens in R23. Also, note that AMD didn't state at what frequency the "pre-production" (not final) Zen4 16 part ran - we have no idea about the ST clock or MT clocks.

You're reading more into the slides than what's actually there.

The slide, nor the footnotes, never claimed that 15% is the minimum ST uplift on an individual application basis. For all we know this could be on an average basis and that the average ST uplift is over 15%.

There's too much ambiguity in the slides to be making anything specific.

I think the best thing to come out of this is the IGPU integration with full-fat Zen 4 desktop cores. Zen 2/Zen 3 APUs have less CPU cache than their full desktop parts and consequently are less performant.

 

[JoeRambo]

If you check the intel 's ADL IPC uplift slide, they have an IPC regression in three workloads:

I strongly suggest You stop for a minute before throwing around word "IPC". Even on Intel slide such word is not found and it's "performance" there. And given their Hybrid architecture and OS scheduling woes i think it is an achievement to have performance regress just in 3 workloads, i've expected a bloodbath.
Zen4 IPC increase is 5-10% cause there is nothing in core for more IPC gain aside from 1MB of L2 and 1.5x L2 TLB. No new major architecture, no 5 ALUs etc. They would show up in GB leak in perf counters etc. Nothing is there.
There will be outliers that love AVX512 or esp love 1MB of L2. And core will make better use of L3 and 3D L3 due to more coverage from TLB reducing average latency.

 

[mikk]

Blender doesn't tell much, we don't have the power settings for the 12900K. Did it run with 241W or strictly according to 125W PL1 and 241W PL2 28 seconds. Also it's hardly a surprise with 16C big cores. 5950X runs only at 4.0 Ghz in Blender and was competitive in this benchmark, if they manage to run Zen4 16C with 5 Ghz most of the gains are coming from clock speed improvements.

Cinebench 1T is more telling and this is a big disappointment. Several in the rumor mill told us Zen 4 increases the IPC by 25% and more and now it looks like Zen 4 is mainly a Zen 3 refresh with DDR5+AVX512 support and bigger L2. No wonder they are pushing the clock speed to new heights, they have to.

 

[JoeRambo]

Cinebench 1T is more telling and this is a big disappointment. Several in the rumor mill told us Zen 4 increases the IPC by 25% and more and now it looks like Zen 4 is mainly a Zen 3 refresh with DDR5+AVX512 support and bigger L2. No wonder they are pushing the clock speed to new heights, they have to.

I think CB 1T is pessimization of core changes they did, as it runs perfectly fine with 512KB of L2. Other workloads will gain more from new L2.
But other than that You are correct. It is refresh of Zen3 core with new IO and AVX512 on new process node.

 

[inf64]

I strongly suggest You stop for a minute before throwing around word "IPC". Even on Intel slide such word is not found and it's "performance" there. And given their Hybrid architecture and OS scheduling woes i think it is an achievement to have performance regress just in 3 workloads, i've expected a bloodbath.
Zen4 IPC increase is 5-10% cause there is nothing in core for more IPC gain aside from 1MB of L2 and 1.5x L2 TLB. No new major architecture, no 5 ALUs etc. They would show up in GB leak in perf counters etc. Nothing is there.
There will be outliers that love AVX512 or esp love 1MB of L2. And core will make better use of L3 and 3D L3 due to more coverage from TLB reducing average latency.

Perf improvement over ISO frequency (terminology used in the intel slide) = IPC, FYI.

Also, how do you know what is in the core? Did you really expect that GB leak will have nitty gritty core uarch. improvements? The core improvements look just like Zen1->Zen2, AMD doubled the L/S capability of the core, beefed up the caches and increased the clockspeeds.

 

[poke01]

Here's the footnote for reference. My apologies if it's a little hard to read.
View attachment 61936

The slide, nor the footnotes, never claimed that 15% is the minimum ST uplift on an individual application basis

But they did claim minimum ST uplift on an individual application basis. AMD used Cinebench R23 vs a 5950X. See the attachment.

 

[coercitiv]

You know perfectly well that power consumption isn't linear with clocks, especially not when trying to push >5GHz across a full 16 cores.

It's obvious I do, that is why I'm questioning your emphasis on perf/w when the current signs indicate that consumer oriented Zen4 SKUs are likely to clock high to compete.

 

[poke01]

So 31% faster with 33% more threads. Raptor Lake is said to feature 32 threads too. 13th gen will be one to Zen 4.

32 threads vs 32 threads. 8 + 16 on Intel vs 16 on AMD.

 

[majord]

That means it did it in 45% less time. It’s 31% faster.

No. you got it the wrong way around.

 

[insertcarehere]

But they did claim minimum ST uplift on an individual application basis. AMD used Cinebench R23 vs a 5950X. See the attachment.

The footnote says that the >15% ST uplift estimate was based on CB R23 vs 5950x. It doesn't say/imply that was the minimum gain they found.

 

[inf64]

The footnote says that the >15% ST uplift estimate was based on CB R23 vs 5950x. It doesn't say/imply that was the minimum gain they found.

Does the footnote state at what clocks did the Zen4 part run? No, there is your clue.

 

[Abwx]

That means it did it in 45% less time. It’s 31% faster.

Seems that you deserted the classrooms quite early...