Why do you pick something from the last 8 years..... two full new uarch , Zen2 having far more Tock in its "Tick" then intel ever did back in its ticktock days. Then there is Zen4 with what ~25% performance over Zen3.Pre-launch BD dividied the forum crowd to two groups:
* the hype train ppl - "all new architecture", "8 cores", "SMT killed by cluster", "FMA4!"
* the IPC fail ppl - "2 ALUs", "0.5 FPU", "16k L1D lmao"
On the other hand, Zen 5 has been hyped to the sky since that weird remark in that interview of AMD's Mr. Clark.
It's odd to see such hype, since you know. Zen 1-4 are definitely very successful designs but... AMD got definitely not a stellar track record of making "brand new things".
K8 was reiterated several times. K9 got cancelled completely. K10 mutated itself after many many years to Bulldozer. Initial 10h was late and plagued with low clocks and bugs. 45nm Bulldozer failed completely. 32nm Bulldozer almost brought the company down. 16h's followup did not make it. That ARM server almost did not make it. Skybridge/K12 got canned.
* the IPC fail ppl - "2 ALUs", "0.5 FPU", "16k L1D lmao"
Of course, it's just a bigger and better Zen in every way. Even L1D latency didn't regress despite 50% size increase.regardless of the other hype, from a purely technical point of view the Zen5 design should not suffer from architectural flaws compared to BD, at least on paper, right ?
(already answered by people with more insight than mine; believe it or not that I was thinking of what they said)What drivers do you think it means?
There are folk out there that have posted large question marks on NVidia's current valuation;
His timing might be somewhat off, but I think the gist is right. Inference will increasingly be done on edge/client hardware. But I'm just a layperson not an analyst.
The clock regression was supposed to happen because Zen 5 was originally supposed to be on 3nm (N3). TSMC (N3) silicon is more energy efficient but sucks at clock speed compared to N5/N4. A bulkier wider core and more bandwidth is not going to affect the max CPU clock speed. AMD will not be on 3nm until a Zen 5 refresh.There will be a clock regression if they run into a thermal wall by widening the core. I expect RPL-S level TDPs for high end GNR.
It is evident that you are far more knowledgeable than to say Zen5 could possibly end up with the same fate as the AMD projects of old.Pre-launch BD dividied the forum crowd to two groups:
* the hype train ppl - "all new architecture", "8 cores", "SMT killed by cluster", "FMA4!"
* the IPC fail ppl - "2 ALUs", "0.5 FPU", "16k L1D lmao"
On the other hand, Zen 5 has been hyped to the sky since that weird remark in that interview of AMD's Mr. Clark.
It's odd to see such hype, since you know. Zen 1-4 are definitely very successful designs but... AMD got definitely not a stellar track record of making "brand new things".
K8 was reiterated several times. K9 got cancelled completely. K10 mutated itself after many many years to Bulldozer. Initial 10h was late and plagued with low clocks and bugs. 45nm Bulldozer failed completely. 32nm Bulldozer almost brought the company down. 16h's followup did not make it. That ARM server almost did not make it. Skybridge/K12 got canned.
Do you mean that AMD will switch over to 3nm when releasing Zen5 X3D, or what kind of other refresh do you mean will happen before Zen6?AMD will not be on 3nm until a Zen 5 refresh.
Problem is there is very little of this available.Maybe we should create a different thread to discuss only the Architectural/technical aspects of this upcoming product with limited speculation ( no hype, no market share discussion, no memes) based on publicly available evidences (patches, GB results, Manuals, official statements)
Yes, this is supposed to be speculation. But there is reasonable speculation and WILD speculation. The latter is frowned on. see aigomorla's moderator post. At this point, and from the leaks we have seen, any mention of bulldozer seems to be WILD speculation.Problem is there is very little of this available.
AMD is keeping everything silent until official announcement it seems. So people get restless and turn to speculation instead. Given the situation, perhaps that's fine, if it's made clear what is speculation vs known fact.
Adroc said dense is like first 3ne customerI thought that someone said that Turin dense is on 3nm
Well, as long as it's made clear what is fact vs speculation. If everything is always stated as 100% absolute certain fact regardless, then you cannot tell what is fact vs speculation.adrock_thurston seems to have believable leaks, but his posts seem more ignored as of late.
Do you think there's any ground behind this quote from the MLID's “source” some month ago?Of course, it's just a bigger and better Zen in every way. Even L1D latency didn't regress despite 50% size increase.
And btw, do you know what the revision of the final silicon is?The original lowball goal for Zen 5's IPC uplift was 20%. And, we thought that would be easy if we put in the work...but it wasn't. We ran into power issues, the shift to 4nm hurt clocks, and at one point we were concerned it might only get efficiency & IPC increases in the low double digits. In fact, we very briefly considered downgrading Strix to Zen 4 to ensure it launched on time.
However, from what I've heard recently, Zen 5 finally has decent optimism behind it.
No, MLID is clueless. GNR and Strix are B0, Turin is C0.Do you think there's any ground behind this quote from the MLID's “source” some month ago?
And btw, do you know what the revision of the final silicon is?
Well, as long as it's made clear what is fact vs speculation. If everything is always stated as 100% absolute certain fact regardless, then you cannot tell what is fact vs speculation.
For cases where it is not fact, some indication on whether the info is just likely, guesstimated, within a range rather than a specific number, or similar would be good.
But there is reasonable speculation and WILD speculation. The latter is frowned on. see aigomorla's moderator post. At this
Inference will increasingly be done on edge/client hardware.
Historically 10-20% uplifts have been more common than bigger ones but past performance is not a prediction of future performance. The BD to Zen uplift was very high, as was the K6 to Athlon and so was P4 to Core 2 and that is just in the x86 space. Apple have seen some huge uplifts so we know it can happen.
Turin customers have been briefed ages ago, and soon infos will be tricked down.Problem is there is very little of this available.
AMD is keeping everything silent until official announcement it seems. So people get restless and turn to speculation instead. Given the situation, perhaps that's fine, if it's made clear what is speculation vs known fact.
Athlon (K7) gave a big boost to IPC only because K6 was quite average compared to the competition (PII), and considering the FP load, very weak. The Athlon K7 with a much larger number of transistors - 22 million (without L2) barely overtook the Pentium III (9.5 million transistors without L2). Especially considering the Socket version, where both microarchitectures achieved the same results.
The situation is similar in the case of Bulldozer vs Zen1 as Excavator in ST had a very weak IPC, which was not a big challenge for Zen1 (2017), which in turn was behind Skylake (uarch) from 2015.
With this in mind, in the past there has not been a huge average increase in IPC compared to the previous generation if the previous generation was already a very high bar.
Zen 4 is not as weak a product as BD and K6.
Intel has the nodes advantage, the man power, the industry connection, the endless pocket. What they managed to do in 10 years with all that is a disgrace. Look at what their competitors have manage to achieve with a fraction of that.You claim that Intel has been stagnant for 10 years, and yet AMD has not managed to significantly overtake uarch. Zen1 barely caught up with Broadwell (Haswell with minor tweaks). If it were that easy, they would have crushed Zen1 by now.
Since 2017, AMD and Intel have been going together like a couple in a dance (Intel sometimes loses its steps a bit).
Are you saying this will suddenly change? I believe that Zen4 is so good that a 40% IPC jump from generation to generation is impossible, considering the project implementation time and the possibilities of the transistor packing process per mm2.
Amd has far more dry powder in terms of architectural resource consumption and they are about to spend it , amd kept up with Intel while doing it with a sizablely smaller core.You claim that Intel has been stagnant for 10 years, and yet AMD has not managed to significantly overtake uarch. Zen1 barely caught up with Broadwell (Haswell with minor tweaks). If it were that easy, they would have crushed Zen1 by now.
Since 2017, AMD and Intel have been going together like a couple in a dance (Intel sometimes loses its steps a bit).
Are you saying this will suddenly change? I believe that Zen4 is so good that a 40% IPC jump from generation to generation is impossible, considering the project implementation time and the possibilities of the transistor packing process per mm2.