isn't ALLthewatts a weibo that got everything wrong , dissapeared for a few days then re-emerged with a new name?Yep, that's what I suspected cause Allthewatt stated the L3 cache of Zen5 and Zen5c are seperated...so we are getting:-
4 x Zen5 CCX1 (16MB L3)
8 x Zen5c CCX2 (8MB L3)
Total 24MB L3 cache
According to All The Watts, it is 16MB + 16MB. Is that correct?Yep, that's what I suspected cause Allthewatt stated the L3 cache of Zen5 and Zen5c are seperated...so we are getting:-
4 x Zen5 CCX1 (16MB L3)
8 x Zen5c CCX2 (8MB L3)
Total 24MB L3 cache
He followed up the tweet with correction....According to All The Watts, it is 16MB + 16MB. Is that correct?
I see, thanks.He followed up the tweet with correction....
All AMD has to do is remember the last decade of the x86 PC space to answer that question. Intel rested on their laurels for years, and it fostered an air of organizational complacency which ruined them. AMD suffered a similar setback back in the Hector Ruiz days when they banked on K8 continuing to dominate Intel and their Netburst architecture.Namely, with Zen 4 being so strong, what is the reason to release Zen 5?
I am more interested on comparison between STX and Qualcomm's X Elite cause they are both launching at the same time and made by N4P process. Surprising, AMD opt for 4P+8E vs Qualcomm's 12 P-cores. Does extra die area give AMD more advantages??That's what it supports, but OEM decides what's in there at the end.
ZEN5 is a lot wider than ZEN4, there's a reason it uses 4+8 Design that probably takes the same space as a 8 ZEN5 Design. 50% more L2, 50% more L3, 2 more WGPs that may also be bigger because of RDNA3.5. Probably more/more modern IO (PCIe 5.0?). Bigger AIE. That's a lot to fit in those 47mm^2, don't you think? It's N4 vs N4(P?) after all.
I am not sure I would call the leaked roadmap "gossip". It has been accurate as far as Hawk Point is concerned.
A leaked roadmap is not as good a source as an official roadmap, but still somewhat above "gossip".
It is not gossip, XDNA2 is indeed comes with Strix Point: Or do you mean Desktop Zen 5???
It lets Microsoft market this:Regarding XDNA, all I have to say to say for now is:
Yep, that's what I suspected cause Allthewatt stated the L3 cache of Zen5 and Zen5c are seperated...so we are getting:-
4 x Zen5 CCX1 (16MB L3)
8 x Zen5c CCX2 (8MB L3)
Total 24MB L3 cache
I had no idea there were instructions missing from Z4 that were included in Alder Lake (which dropped (but not really) AVX512).
AMD should not be stupid enough to make such a config. I't unbalanced CCX configuration which makes thread scheluding absolutely nightmare as for 5 thread job has to choose core per thread from different CCX:s or switch to low-speed CCX.
Have you seen benchmarks for that yet? I don't think anything has leaked in that regard.On topic of two different CCX -> it is as bad as any other hybrid
But what non-server CPUs are in that list ? Zen 4 is the only one unless I missed something.I had no idea there were instructions missing from Z4 that were included in Alder Lake (which dropped (but not really) AVX512).
AMD is stupid enough, never doubt it. They disgraced themselves by releasing abomination Threadripper where half of NUMA nodes had no direct connection to memory, so nothing is too stupid for them. There is no redemption for that, straight to hell.
Oh please, that was one gen of Threadripper and it worked fine anyway.
I think it was working fine in Cinebench. Anywhere else ran the risk of hitting crazy concurrency problems:
63 Cores Blocked by Seven Instructions
I seem to have a habit of writing about super powerful machines whose many cores are laid low by misuse of locks. So. Yeah. It’s that again. But this one seems particularly impressive. I mean, how …randomascii.wordpress.com
But i guess it was AMD's way to prepare us all for very parallel future, release as retarded product as possible to exposes such weaknesses before launching 64C chips.
On topic of this new chip -> i don't have any problems with it and it will perform great beyond typical scheduling woes. ZEN5C even with reduced clock is lots of perf.
Still, let's not underestimate AMD's stupidity like @naukkis did, they surely can release lazy and stupid products.
Only a few people bought those things. And they certainly knew what they were getting into before they bought it.
Anywhere in crazy Windows scheduler land you mean. All it showcased is how bad and woefully unprepared the Windows scheduler is. You should complain more to Microsoft instead.Anywhere else ran the risk of hitting crazy concurrency problems: