Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[jpiniero]

Nope.

Have you ever thought that perhaps the boost clock speeds on Epyc might be a lot higher?

 

[gdansk]

Either it hits the claimed figure or it does not, there is no wiggle room on it.

It's true for Product X with power limit increase but not Product Y without power limit increase.
In any case, that specific claim is itself also possibly a cherrypicked good result. It's better than GB but still contains some easily broken benchmarks.

 

[APU_Fusion]

Boy, the angry people on thread now calling Zen 5 bulldozer 2.0 right now is amusing. Enjoying Tears of disappointment? I mean really? 🙄

Zen 5 will be as fast as it is. It isn’t actually a living being, AI aside ..

 

[adroc_thurston]

Have you ever thought that perhaps the boost clock speeds on Epyc might be a lot higher?

Nope.

I don't know if there is anything new here, or just summary of the "consensus"

https://twitter.com/x/status/1788507350707617897

This is all kinds of wrong, GPU clocks in particular.

Boy, the angry people on thread now calling Zen 5 bulldozer 2.0 right now is amusing. Enjoying Tears of disappointment? I mean really? 🙄

LNC is a catastrophe so they want to make Z5 one too.
Sad!

 

[Fjodor2001]

yea.
yuo can see in on the floorplan.

Well, w.r.t. performance improvement, Zen1 did much better than Zen3. So if the redesign was as big with Zen3 as Zen1, then the changes made in Zen3 were not as effective at least.

 

[adroc_thurston]

Well, w.r.t. performance improvement, Zen1 did much better than Zen3.

Z1 was a finfet shrink (i.e. area constraints are somewhat secondary) and a jump off a real bad baseline.
Zen3 isn't that.

then the changes made in Zen3 were not as effective at least.

It was very very good at IPC:Cac and IPC:area metrics.

 

[AMDK11]

Intel had a massive headstart in architecture, node and OEM support. It should have been impossible for AMD to catch up let alone surpass Intel on what looks to be all 3 fronts. They have done so through Intel utterly screwing up on multiple sides and by AMD taking a leaf out of NVs book and becoming an execution machine.

Zen 5 is the 1st ground up design where AMD have had decent R & D money. They could squander it of course but given their execution record over the last 7 years I don't think they will.

Compared to other designs I don't think Zen 4 is that great, it is simply the least bad x86 design

Does a project from scratch have to mean such a large expansion that the project achieves an average of 40% higher IPC?

I think you are overestimating the phrase "new project from scratch".

A new greenfield project can also average 10-15% higher IPC.

Apple, they did many 20-30% IPC increases in a row despite already having the best core.

Apple had no competitive pressure. It is safe to say that there was stagnation in terms of core expansion and the industry reacted with a delay anyway.

Moreover, Apple provides only a few large cores for its systems, while AMD and Intel must take into account the core + cache area not only for consumer processors but also for Epyc and Xeon. Intel and AMD need to saturate a larger part of the market with their systems, and here the number of wafer chips plays a key role. You still need to balance the expansion of the uarch, IPC gains and the number of systems.

Apple had time, and AMD and Intel, competing with each other, do not have the time that consumes not only the design but also implementation into silicon.

Why is Apple now giving modest IPC profits and not +30% again?

 

[adroc_thurston]

Does a project from scratch have to mean such a large expansion that the project achieves an average of 40% higher IPC?

yea.

I think you are overestimating the phrase "new project from scratch".

Nope.

A new greenfield project can also average 10-15% higher IPC.

Depends on the timeline, people and power/area constraints involved.

Apple had no competitive pressure

YES THEY DID.
They've built their chungus core lineage to distance itself from the android mainstream on raw performance metrics.
The selling point of every iPhone since 5s was chungus core.

while AMD and Intel must take into account the core + cache area not only for consumer processors but also for Epyc and Xeon

AMD cache layouts are shared between client and server (well, *were* shared).

Why is Apple now giving modest IPC profits and not +30% again?

Because it's a skeleton crew with most Big and Relevant people who drove their roadmap leaving to greener pastures (Nuvia, Rivos, AMD, etc).

 

[Joe NYC]

I'm guessing the 10%ers are as wrong as the 32%ers
I don't think either side will be crying but cherrypicking.

When it comes to forecasting, I used to read The Economist for years and years, and near the end of the magazine, they used to have (maybe still do) forecast for GDP growth for major (or notable) economies of the world. This was the average / consensus of economists who are being paid big bucks for these "forecasts"

It didn't take too long to crack the code. For every country in the world, they had a "target" of ~2%, and if the country was below, the forecast for the following 2 years was to inch up to the range, if it was above, it would slow down to the target.

It seems that something similar is happening here. It is considered to be smart to be in the middle of the herd, and there is a lot of derision to those outside of the safety of the herd.

 

[Timorous]

It's true for Product X with power limit increase but not Product Y without power limit increase.
In any case, that specific claim is itself also possibly a cherrypicked good result. It's better than GB but still contains some easily broken benchmarks.

Specint 2017 1t shouldn't be impacted by power constraints being a single threaded test.

It does not matter if Specint is a good showing Vs the geomean, the claim cites a specific benchmark suite with a specific thread count. It is on that basis alone it should be judged. If the Specint uplift does not translate to the average then so be it but that is a separate thing.

 

[Fjodor2001]

Z1 was a finfet shrink (i.e. area constraints are somewhat secondary) and a jump off a real bad baseline.
Zen3 isn't that.

Yeah, well. Coming back to Zen5, Zen4 is not such a bad baseline.

So if Zen5 should be able to bump IPC 40% or perf 45+ % (various numbers have been speculated by various people) over Zen4, that would be much harder than it was for Zen1.

 

[adroc_thurston]

Zen4 is not such a bad baseline.

Ehhhh it's rather skinny in many places by modern standards.
Only opcache is sized akin to modern trends there.

that would be much harder than it was for Zen1.

Ambition tamed by execution discipline is how you run a good roadmap.

 

[jpiniero]

Specint 2017 1t shouldn't be impacted by power constraints being a single threaded test.

But the max boost clock on most of the Epyc lineup is very low.

 

[gdansk]

It does not matter if Specint is a good showing Vs the geomean, the claim cites a specific benchmark suite with a specific thread count. It is on that basis alone it should be judged. If the Specint uplift does not translate to the average then so be it but that is a separate thing.

Then let me rephrase my post for you: who thinks Zen 5 is 32% faster in general is likely as wrong as people saying 10% faster in general. And no amount of cherrypicking specific benchmarks will make either right in general based entirely on past performance.

Specint 2017 1t shouldn't be impacted by power constraints being a single threaded test.

On Weibo they say top end EPYC will be going from 1T 3.7GHz to 1T ≥4.3GHz...
This isn't the case on desktop, where clock speeds are likely to be the same or very close. Or mobile, where it seems there may have been a minor regression.

 

[Joe NYC]

This is all kinds of wrong, GPU clocks in particular.

No, that's impossible. RDNA 3 is what it is, and it is unfixable.

Anyone thinking otherwise, is still falling for the same "hype".

 

[GTracing]

It seems to me whether or not Zen5 is a ground-up design or not is mostly academic, and has no impact on the performance we should expect from it. Zen3's performance improvement was not any bigger than Zen2 or Zen4, despite being a ground-up redesign.

 

[Fjodor2001]

who thinks Zen 5 is 32% faster in general is likely as wrong as people saying 10% faster in general.

Are we down to only 32% now? Previously it was 40-45+%, what happened to that? And where does the 32% number come from?

 

[Timorous]

But the max boost clock on most of the Epyc lineup is very low.

On Weibo they say top end EPYC will be going from 1T 3.7GHz to 1T ≥4.3GHz...

That affects IPC how?

Clocks will determine final performance but IPC claims are not impacted by final clockspeeds.

For desktop Zen5 the thought is that final clocks are similar to Zen 4 clocks so performance and IPC are practically synonyms but if we are talking laptop or server then performance can vary quite a bit more than the IPC figure.

 

[gdansk]

That affects IPC how?

Clocks will determine final performance but IPC claims are not impacted by final clockspeeds.

For desktop Zen5 the thought is that final clocks are similar to Zen 4 clocks so performance and IPC are practically synonyms but if we are talking laptop or server then performance can vary quite a bit more than the IPC figure.

Who is talking about IPC? They care about 1T. The claims regarding SPECint were not at a iso frequency, rather "core to core". Then later they also say clock rate isn't increasing or maybe worse (but this is only true for some products).

 

[CouncilorIrissa]

Are we down to 32% now? Previously it was 40-45+%, what happened to that? And where does the 32% number come from?

We're not "down" anything.
There never was a 45%+ claim, the claim from Kepler was 40% faster in SpecInt 1T per core.
Adroc's claim has always been 32% IPC iso/clk.

But nice attempt at setting up a narrative.

 

[Timorous]

Who is talking about IPC? They care about 1T. The claims regarding SPECint were not at a iso frequency, rather "core to core".

That was the 40% claim. The original 32% claim from a long while ago was IPC.

 

[AMDK11]

Nope.

This is all kinds of wrong, GPU clocks in particular.

LNC is a catastrophe so they want to make Z5 one too.
Sad!

Any tests? At what clock speed? No one is going to change what Zen 5 and LionCove are by saying positively or negatively about the uarch they choose.

Interestingly, however, seeing an increase in only two points of the architecture from 6 to 8 (+33%) Dispatch/Rename and from 4 to 6 (+50%) ALU, an average IPC increase of 40% is already assumed, because it is a "new project from scratch.
AMD in Zen 5 added 2 execution ports 1 for ALU and 1 for AGU.

Not taking into account that AMD has added some resources here and there by redesigning the core, but the rest of the optimization and expansion will be done in the next generation of Zen. If Zen5 has an average +15-20% higher IPC, it will be a good generational gain.

If it's an average of 25-30% higher IPC for Zen5, I think everyone will be happy, including me.

If there is a small IPC gain after such a major redesign of the LionCove core and adding so many resources, I will criticize ArrowLake because it will be a waste of Intel's time spent on the project. Unless Intel didn't try at all and the project was done half-heartedly.

 

[Fjodor2001]

We're not "down" anything.
There never was a 45%+ claim, the claim from Kepler was 40% faster in SpecInt 1T per core.
Adroc's claim has always been 32% IPC iso/clk.

But nice attempt at setting up a narrative.

Well, some reasoned that the 40% SpecINT would also be representative of perf increase in general. Then some added possible 5+% clock bump on top of that. So we were at 40-45+% perf increase.

 

[gdansk]

That was the 40% claim. The original 32% claim from a long while ago was IPC.

I see. I'm talking about 1T performance, not IPC. I needed to choose a number equally far from 21% (an average of AMD's past performance) as 10% was. That it happens to be 32% is a coincidence.

 

[PJVol]

In a way that people who designed it disagree with you, and I tend to believe them more:

I'm not keen on discussing the bold headlines that you apparently considered indisputable evidence. As for the rest of the slides, they are not much different from the Zen 2 ISSCC, for example

The Zen 2 design has numerous design improvements over Zen (Fig. ^^^), including a 15% instructions-per-cycle (IPC) improvement on an average single-threaded application, while reducing the technology-neutral switched capacitance-per-cycle (CAC) by 9%

in addition to
- Package routing challenges
- Under-CCD routing
- VDDM distribution
- Package integration
- L2/L3 macros changes
- Per-core and VDDM dLDOs
- new fabric design
- two more metal layers plus MIMCaps

Adding to this the design of the CCX on a completely different node (GF14LPP > TSMC 7nm), I'm just wondering, do you think this is really less "ground-up" task?
While I agree that CCX changes are more significant in Zen 3 and Zen 2 CCX is hardly considered "from the scratch", but for the CPU as a whole, I see Zen 2 as a bigger step and more work was put in, and btw I'm not asking you or anyone else to believe me.