I predict there will be predictions about IPC.Nah, thats too specific to win the thread.
I predict IPC.
I know. I predicted you would be inclined to do so.I predict there will be predictions about IPC.
Btw, it is interesting AMD is so tight-lipped not only about performance, but also about architecture.
That USUALLY means good, or very good news.Btw, it is interesting AMD is so tight-lipped not only about performance, but also about architecture.
Teach me the secrets of the industry, Master.That USUALLY means good, or very good news.
Bad news spread with the speed of light in this industry. Good news are always kept secret to the very end.
When writing about research and teaching throughout the entire period of work on Zen 1-4, I mean that not all developed solutions were implemented, but left to subsequent generations.That's pretty raw cope.
Solutions and very large milestones either translate into large IPC increases or you're ARM Austin/Sofia. And you suck.
that's not how semicon pathfinding even works.
the new bits of Zen5 have like, 0 relation to previous Zens, that's the point.
They're not learnings, but novel crackpot concepts of doom.
It is actually pretty easy. One of the closed source CN RISC-V cores coming out soon-ish will be CMT-based. However, it is based more on the older clustered patents rather than the newer dual-core processor patents. With additional stuff like Gracemont's front-end and Zen3/Zen4's FPU, etc.Is it impossible to design power efficient CMT cores?
It's 15% total for all the iphone/mac/whatever N3 revenue.The A17 Pro isn't that small... there's a reason that N3 was 15% of TSMC's revenue in their last quarter. Probably in the low 100 range.
Most are.When writing about research and teaching throughout the entire period of work on Zen 1-4, I mean that not all developed solutions were implemented, but left to subsequent generations.
Yeah it is.A microarchitecture that will result in a huge average IPC increase is not necessarily a breakthrough or milestone for AMD
Bloat in vacuum doesn't do much, see Intel.AMD has no choice but to expand the core to enable further IPC gains.
Jesus that's like every Zen since Zen1.and I don't think new techniques will suddenly result in huge increases in IPC without a large increase in transistor counts.
They're not expectations, no.I understand you have high expectations for the Zen5's mid-range IPC gain
x86 land sucked at IPC bumps.because there has practically never been such a large average jump in x86 IPC from generation to generation
Turin perf numbers are kinda public domain knowledge.Until strong evidence and verification emerges,
It's 15% total for all the iphone/mac/whatever N3 revenue.
Most are.
That's how semis R&D works.
Yeah it is.
Bloat in vacuum doesn't do much, see Intel.
Jesus that's like every Zen since Zen1.
Nothing's gonna change.
They're not expectations, no.
x86 land sucked at IPC bumps.
Look somewhere else.
Turin perf numbers are kinda public domain knowledge.
I don't know if there's coming clustered - split register file - risc-v design but it's sure that risc-v even considered to split registers in ISA level. They choose to use non-split register model but still design their ISA clustering friendly. And it's pretty obvious that very wide high clocking - best performing - cpu designs someday will be somehow clustered designs. From old studies it's found that clustering will lower IPC compared to equal wide non-clustered design so when clustered designs come it probably will be right away about twice as wide design compared to non-clustered.It is actually pretty easy. One of the closed source CN RISC-V cores coming out soon-ish will be CMT-based.
aka stuff that's never gonna happen.support needs to be done at compiler-level
aka stuff that's never gonna happen.
you're welcome.
that's not happening.So basic clustering example - split 32 physical registers to 4 8 register groups. Make compiler to produce 4 different code paths withing thread using those 8 register sets. Heck - risc-v even have compressed instruction format for 8-register use cases, they just need to invent some hint for hardware to expand that 4-way clustering.
Any particular reason to not chase that quite low hanging fruit to path for very wide cpu-core designs?that's not happening.
Because you don't want to put things in your ISA that require recompilation to benefit from them.Any particular reason to not chase that quite low hanging fruit to path for very wide cpu-core designs?
Because whacko ISA design gimmicks are so 1990.Any particular reason to not chase that quite low hanging fruit to path for very wide cpu-core designs?
Bingo, stuff should work ootb or it's useless.Because you don't want to put things in your ISA that require recompilation to benefit from them.
Isn't that what nvidia gpus do, MIMD?So basic clustering example - split 32 physical registers to 4 8 register groups. Make compiler to produce 4 different code paths withing thread using those 8 register sets. Heck - risc-v even have compressed instruction format for 8-register use cases, they just need to invent some hint for hardware to expand that 4-way clustering. Simplest thing to come mind is just pack two of those 16bit instructions in 32 or 64 bit instructions.
That's what all GPUs do.Isn't that what nvidia gpus do, MIMD?
Isn't that what nvidia gpus do, MIMD?
Because you don't want to put things in your ISA that require recompilation to benefit from them.
again, leave whack ISA clownage in the 90s.That's pretty ridiculous statement. What they need to think about that code is executable both non-clustered and clustered designs - which might be quite challenging.
again, leave whack ISA clownage in the 90s.
We're far past that.
No?ARM and x86 are adding instructions for every possible side-case
That's worse.Risc-v is better but even there is million proposals to add very hardware-specific instructions
Please leave schizo esoterica in 1990s.And ISA does not have to support clustering - compiler can cluster every ISA as it wants( only practical with enough hardware registers) and Risc-V so far have not added any clustering-specific instructions - only have kept path for clustering open for not implementing instructions that makes clustering difficult
Please leave schizo esoterica in 1990s.
It's not coming back. Ever.
No?It's already here
No?Hardware tries to split code to concurrently executable clusters
Anything not bog standard ISA doesn't work.Epic failures happen for making things too complicated - I think that they didn't even publish any hardware with clustered execution.