Discussion Dimensity 9300; The end of an era for the Cortex A5xx core?

FlameTail

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The Mediatek Dimensity 9300, the succesor to the Dimensity 9200 will apparently released soon in the coming months. Till then, we have has several leaks about this chip and they paint an interesting picture.

The CPU of the Dimensity will apparently have a configuration of 4 Cortex X4s + 4 Cortex A720s. There is no Cortex A520 or any other Cortex A500 series core.

This leak was discussed in this reddit thread
I myself thought that such a configuration would be an inefficient thermal disaster, but the insight obtained from reading the above thread proved otherwise.

They speculate that the D9300 will have a single Cortex X4 core clocked at high speeds (3 GHz+) and the 3 other cores will be low-configured Cortex X4s with less caches and lower clockspeeds.

Apparently these 3 low-config Cortex X4s will carry the multicore performance. They mention how such a low-config Cortex X4 is actually more efficient than a high-config A720 (running at high clock speeds; 2.8GHz+, which is what SoC vendors have been doing for a long time). This is possible because the Cortex X4 cores have a wide design with higher IPC than the A720.

Speaking of the A720, we come to the other 4 cores of the Dimensity 9300. Apparently these A720s will be the low-config ARM unveiled at TC2023, running at a clock speed ~2 GHz. These four A720 cores will spiritually replace the four Cortex A510 "efficiency" core used in previous designs. This configuration of four A720 cores is similar to that in Apple's Bionic chips. The redditors mention the A720 can serve the purpose of an "efficiency" core well, although one person notes that the A720's leakage below 0.5 GHz will destroy it's efficiency.

Thus, the Mediatek Dimensity 9300 might represent the beginning of a new era, where the Cortex A5xx are no longer a Smartphone SoCs efficiency cores.

What are your thoughts on this?
 

NTMBK

Lifer
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Good. A52 and it's descendents are trash, and I'll be glad it I never see another one with 8 in-order cores and no decent CPUs.
 

hemedans

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Jan 31, 2015
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Evan Blass said D9300 has Overheat problems, Mediatek deny this rumor but there may be some truth, all D9000 series has serious standby issues i dont see how this configuration would help them, unless they target Laptop market, Soc like 9200+ can use as much as 17W, this is going to surpass that.
 

FlameTail

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Remember this post I made? I think it's relevant to the current discussion

 

ikjadoon

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Sep 4, 2006
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Arm itself allows licensees to switch some X4s to a "Low Performance Configuration", which can notably decrease the core's total area by halving vector datapaths & just a quarter of the maximum L2 (2MB → 512KB).

Stand-alone instantiation of Cortex-X4 Low Performance Configuration ( VEC - 2x128b / L2 512K ) is prohibited. Cortex-X4 Low Performance Configuration ( VEC - 2x128b / L2 512K ) must only be used alongside at least one instance of Cortex-X4 Higher Performance Configuration ( VEC - 4x128b / L2 minimum 1M ) and always in the same cluster. Failure to comply to this requirement equals a non-compliant Arm product. For more details, please refer to the Cortex-X4 Release Note.

...

L2 cache size
You can configure the L2 cache to be 512KB, 1024KB, or 2048KB. The cores in the cluster can have different cache sizes.

I like MediaTek's idea, but the cost in licensing & fabrication (as Cortex-X4 is still a relatively large core) seems like a big jump.

IIRC, Arm's licenses are per shipped core (not type of core) and the Cortex-X are the priciest. But, it will allow MediaTek to confidently claim the SoC performance crown, where Qualcomm has routinely—but not always—taken. So maybe it's worth it, especially if MediaTek can score a big node advantage.
 

FlameTail

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Arm itself allows licensees to switch some X4s to a "Low Performance Configuration", which can notably decrease the core's total area by halving vector datapaths & just a quarter of the maximum L2 (2MB → 512KB).



I like MediaTek's idea, but the cost in licensing & fabrication (as Cortex-X4 is still a relatively large core) seems like a big jump.

IIRC, Arm's licenses are per shipped core (not type of core) and the Cortex-X are the priciest. But, it will allow MediaTek to confidently claim the SoC performance crown, where Qualcomm has routinely—but not always—taken. So maybe it's worth it, especially if MediaTek can score a big node advantage.
Not only the X4 core, even the A720 has an official lower configuration as ARM presented it In TCS2023. I guess the Dimensity is using this.

Well if the aforementioned argument holds true, then Mediatek will claim not only the performance crown, but the efficiency crown too.
 

soresu

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Dec 19, 2014
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Not only the X4 core, even the A720 has an official lower configuration as ARM presented it In TCS2023. I guess the Dimensity is using this.
Yes the A720 has a lower perf config that is just 10% higher IPC than A78 at iso area and power.
 

soresu

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Dec 19, 2014
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Also Apple E cores use way less power, A720 need to be 300-500% more efficient to be used like Bionic Configuration
Going by this chart A15E is significantly less than 300% more efficient (243%?) than the D1200's mid A78 despite A15 being fabbed on a significantly better process node (N5P vs N6).

Obviously this chart is not a great representation of the current intrinsic µArch efficiencies given that this is at least 1-2 gens out of date on both sides and not iso process.

Would be nice to see A715 vs A16E on a similar process node.
 

Panino Manino

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What about SMT? Will phones eventually start using the feature?
The Kirin 9000S remains mysterious, but some people claim it's big cores have SMT? After updates Antutu reports 12 "cores".
 

FlameTail

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Going by this chart A15E is significantly less than 300% more efficient (243%?) than the D1200's mid A78 despite A15 being fabbed on a significantly better process node (N5P vs N6).

Obviously this chart is not a great representation of the current intrinsic µArch efficiencies given that this is at least 1-2 gens out of date on both sides and not iso process.

Would be nice to see A715 vs A16E on a similar process node.
Wait, so is Apple E even more performance than Cortex A7xx?
 

soresu

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What about SMT? Will phones eventually start using the feature?
The Kirin 9000S remains mysterious, but some people claim it's big cores have SMT? After updates Antutu reports 12 "cores".
Cortex A65/Neoverse E1 used SMT, but it never had any consumer applications as far as I am aware.

The fact that ARM went with a CMT type µArch instead with A510 says that they decided to go in another direction.
 
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soresu

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Wait, so is Apple E even more performance than Cortex A7xx?
More perf/watt, but not more raw perf - not even close going by A78/A15E.

Though gains from A710 -> A720 have been smol for 3 generations, A720 is only just catching up to X1 now in the X4 generation.

So A17E could very well have met or exceeded A7xx perf at this point.
 
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soresu

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Hmmm, now that I look at this graph further I see the S865 A77 Prime has an even better efficiency than the D1200 mid A78.

N7P S865 = 6,658J % 3.59 Spec points = 1,854J / Spec point.

Then account for the 0.661111x power node difference between S865's N7P and A15's N5P: 0.661111 x 6,658J = 4,401J.

Node normalised perf/watt:

S865 A77 = 4,401J % 3.59 Spec points = 1,226 J / Spec point.

A15E = 2,349J % 2.42 Spec points = 970J / Spec point.

A15E still ahead by a good margin, but not nearly so bad as 300-500%.

My math on this may be entirely wrong so please explain my mistakes if so 😅

Edit: I know that process node gain figures are idealised, but it's all I have to work with.
 
Last edited:

Bigos

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I don't think SPEC is a workload with fixed time - it has fixed work instead (the faster the CPU, the quicker it finishes). So you should not divide the energy consumed by the number of points as the score is inversely proportional to the time the SPEC run took. The energy consumed is inversely proportional to the energy efficiency (the less energy consumed the more efficient the computation), so just take 1/W (W = work = the number of Joules) to get the energy efficiency.
 

soresu

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I don't think SPEC is a workload with fixed time - it has fixed work instead (the faster the CPU, the quicker it finishes). So you should not divide the energy consumed by the number of points as the score is inversely proportional to the time the SPEC run took. The energy consumed is inversely proportional to the energy efficiency (the less energy consumed the more efficient the computation), so just take 1/W (W = work = the number of Joules) to get the energy efficiency.
I'll take your word if you can translate that into figures for me 😅
 
Sep 18, 2023
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How about ARM's performance curves?



It shows how Cortex X4 can offer significantly higher performance than the A720 at its peak.

A520 only covers the power curve in very low-performance scenarios.

Also, consider that Apple's Big Core is a GIANT Core, is much larger than Cortex X3 & X4, and Apple's efficient core is somewhere in between the size of the A700 series and the Cortex X-series.

Apple's SOC is more a 2+4+0 when compared to previous Cortex-based 1+3+4 of the Mediatek 9200.

And When compared to Qualcomm's 1+3+4+3 configuration of the 8 Gen 3; Mediatek's 9300 is going to be a 1+3+4+0.

Just as the Wider Qualcomm's 1+4+3 was more efficient than the 1+3+4 of the 9100/9200; I expect the wider 9300 will be more efficient than the 8 gen 3.

However, the big advantage I would like to see with the 9300 is using the same die for both smartphones, and for tablets and chromebooks featuring a higher TDP
 

FlameTail

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Can someone do a IPC comparison between X4, A720 and A520?

If that is known, we can have a preliminary guesstimate at the performance of the D9300 and SD8G3, since we already know their configurations: 1+3+4+0 and 1+0+5+2
 

StinkyPinky

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Apple must use pixie dust, they always seem a few generations ahead.

Athough the rumor mill is that 8 Gen 3 is a beast. Hopefully so. Heard that before though.
 
Sep 18, 2023
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To be fair, ARM has not performed well in their A700 and A500 series designs as of late. The A715 design is only marginally better than the 2020-A78, which is an improvement over the A77 but not by a significant amount (A78 PPA > A77).

Moreover, the A510 design is also disappointing as there have been no improvements in the design for years. It's such a small IOE design that it only covers a tiny fraction of the energy curve, and it doesn't represent a significant loss for OEMs. Apple's E cores are much larger compared to the A500 and are mostly comparable to the A700 series.
 
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FlameTail

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Google is going to use a single X core in the Tensor G3, abandoning their stint with the 2-X core design in the original Tensor and Tensor G2.

What implifications does this have?

Do you guys consider Google's stint with 2-X cores was 'succesful' ?
 
Sep 18, 2023
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Google is going to use a single X core in the Tensor G3, abandoning their stint with the 2-X core design in the original Tensor and Tensor G2.

What implifications does this have?

Do you guys consider Google's stint with 2-X cores was 'succesful' ?

I think it was a relic of the original Exynos design with two Mongoose cores. Supposedly, it can allow more fluid multitasking performance.

With a competent node, however, the A78 can provide a very competitive performance while being drastically more efficient, like the Dimensity 8000/8100/8200 shows.

By now, the 4-core cluster with A700 can finally be up to the task. I'm afraid that the Samsung node won't allow for much, if any, increase in single-threaded performance, that's what's mostly pulling Google back, but you are right that the 4-core A700 can provide better battery life at the least. Can't wait for the reviews.
 
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