Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

 

[Markfw]

Intel obviously has design team problems as well, with Sapphire Rapids requiring 12 steppings to get right.

And still losing badly to Genoa/Bergamo

 

[igor_kavinski]

When it comes to totally screwing the company, Kraznich & Bob Swan hold the crown! World's top two visionaries!

I think Swan can be excused for being put in the wrong position coz he was just a finance guy but Krzanich was actually a fab management guy and he destroyed Intel's fab dominance in his tenure. I mean, he gets the award for "Best way to F up at your job despite having the core competency to excel at it!".

 

[FlameTail]

I think Swan can be excused for being put in the wrong position coz he was just a finance guy but Krzanich was actually a fab management guy and he destroyed Intel's fab dominance in his tenure. I mean, he gets the award for "Best way to F up at your job despite having the core competency to excel at it!".

Now we to find the guy responsible for crashing Samsung'a fab in the past few years.

They fumbled 7nm, 5nm, 4nm and now seemingly 3nm as well.

 

[igor_kavinski]

Now we to find the guy responsible for crashing Samsung'a fab in the past few years.

Him: https://gizmodo.com/samsung-lee-jae-yong-prison-acquittal-2015-merger-1851225005

 

[SiliconFly]

Intel obviously has design team problems as well, with Sapphire Rapids requiring 12 steppings to get right.

Previously, the design & foundry teams had way too much inter-dependencies leading to massive delays. But then, Jim Keller stepped in and sorted it out. The design teams now have to operate only with pdks. Actually, this was quoted as the main reason that caused too much friction that eventually led to his exit. As of now, the design teams operate completely independently of the nodes. And all upcoming core designs are node agnostic. i.e, they can now quickly and easily iterate, validate, test & release at a much faster pace.

 

[FlameTail]

https://twitter.com/x/status/1764916192480018859

[Exclusive] Samsung has decided to change the name of the '2nd generation 3nm' process to '2-nanometer.' In other words, the plan is to refer to the 2nd generation 3nm process, which will be mass-produced this year, as '2-nanometer' going forward.

According to a source quoted by ZDNet Korea, "We were informed by Samsung Electronics to change the 2nd generation 3-nanometer to 2-nanometer," and added, "Last year, we contracted with Samsung Electronics Foundry for the 2nd generation 3-nanometer, but recently we re-wrote the contract under the name of 2-nanometer."

It is practically understood that Samsung Electronics recently secured orders for AI accelerator chips based on the 2-nanometer process from the Japanese AI startup PFN (Preferred Networks), which are essentially identified as utilizing the 2nd generation 3-nanometer process. These chips are scheduled for mass production in 2025.

Node renaming shenanigans again....

But there is a difference.

When Intel renamed their 10nm to Intel 7, it was kinda justified, because Intel 10nm actually had slightly better density than TSMC 7nm.

But this move by Samsung is not just justifiable. Their 3nm GAA already has worse density than TSMC 3nm FinFET. Renaming their 3nm to 2nm means the gap is going to be even wider when comparing TSMC 2nm and Samsung 2nm.

 

[igor_kavinski]

And all upcoming core designs are node agnostic. i.e, they can now quickly and easily iterate, validate, test & release at a much faster pace.

Not that quickly I'm afraid. Otherwise we wouldn't have stale Raptor Lake Refresh. Would have been really nice to have monolithic MTL on Intel 7+++.

I mean how is this acceptable for Intel INSIDE their HQ: https://www.techpowerup.com/317317/...res-show-ipc-regression-over-raptor-lake?cp=4

 

[DrMrLordX]

Node renaming shenanigans again....

Is this 3GAP that's being renamed? Perhaps Samsung is taking advantage of perceived weakness of TSMC's N3B process; however, 3GAP probably isn't much better (if at all).

 

[igor_kavinski]

Samsung 2nm.

It just lets their customers advertise 2nm process in marketing materials. Not the first time marketing folks get to distort the truth.

 

[igor_kavinski]

Is this 3GAP that's being renamed?

I would hope so. 3GAP sounds bad just looking at it. 3 GAP, as in 3 gaps in it!

 

[FlameTail]

Idk if it is 3GAP or 3GAP+

 

[igor_kavinski]

Is there mobile silicon out using 3GAE?

 

[DavidC1]

But this move by Samsung is not just justifiable. Their 3nm GAA already has worse density than TSMC 3nm FinFET. Renaming their 3nm to 2nm means the gap is going to be even wider when comparing TSMC 2nm and Samsung 2nm.

That's why they also lost previous generation comparisons pretty badly because "shrinks" for Samsung were often just plusses.

The old Intel joke of 14nm = 14nm, 14nm+ = 13nm 14nm++ = 12nm applies here.

 

[FlameTail]

Is there mobile silicon out using 3GAE?

None.

Exynos 2500 coming 2025 January will probably be the first to use SF3 (3GAP).

 

[Tigerick]

None.

Exynos 2500 coming 2025 January will probably be the first to use SF3 (3GAP).

And if I understand above tweet correctly, it will be called 2-nanometer or SF2 ???

 

[SiliconFly]

Not that quickly I'm afraid. Otherwise we wouldn't have stale Raptor Lake Refresh. Would have been really nice to have monolithic MTL on Intel 7+++.

I mean how is this acceptable for Intel INSIDE their HQ: https://www.techpowerup.com/317317/...res-show-ipc-regression-over-raptor-lake?cp=4

View attachment 94862

Lol. A few months back I did mention MTL may have a slight performance regression. But I got battered for saying that.

 

[Hitman928]

Lol. A few months back I did mention MTL may have a slight performance regression. But I got battered for saying that.

I am skeptical of his testing. Another reviewer found no IPC difference between MTL and RPL P-cores with SPECint. I believe the other reviewer used laptops that both had the same type of memory as well, unlike this testing. Both use fast enough memory that it shouldn't effect the score much, but enough to get a 5% shift? Maybe.

Edit: This is the same reviewer that listed LP P-cores in their testing (which doesn't exist) and showed an IPC regression in the E-cores as well whereas Intel said they improved E-core IPC. Now, I don't necessarily take Intel at their word, but the other reviewer I mentioned did show an IPC increase in their testing of the E-cores, right in line with Intel's IPC claims. All of this leads me to believe this was simply faulty testing and there is no IPC regression in the P-cores and an IPC increase in the E-cores, which is basically what Intel said themselves.

Edit2: He also has entries like this in his table of SPECint scores:



How do you calculate IPC from a score if you don't know what the actual clock rate was when running the benchmark? Did he actually track the average clock speed or just use the mid point of his range (which would most likely be inaccurate for IPC calculation)? Too many questions and things that don't add up for me to trust his testing.

 

[SiliconFly]

https://twitter.com/x/status/1764916192480018859

Node renaming shenanigans again....

But there is a difference.

When Intel renamed their 10nm to Intel 7, it was kinda justified, because Intel 10nm actually had slightly better density than TSMC 7nm.

But this move by Samsung is not just justifiable. Their 3nm GAA already has worse density than TSMC 3nm FinFET. Renaming their 3nm to 2nm means the gap is going to be even wider when comparing TSMC 2nm and Samsung 2nm.

All these "nm" don't make sense anymore. It's been more than 20 years since node names actually represented transistor metrics. In Intel 20A, TSMC N2 & Samsung 2nm, the actual transistor is actually around 10X bigger (or more) I think. All these 20A, N2, SF2 are pure marketing tricks. I don't think we should take them seriously anymore going forward.

 

[SiliconFly]

I am skeptical of his testing. Another reviewer found no IPC difference between MTL and RPL P-cores with SPECint. I believe the other reviewer used laptops that both had the same type of memory as well, unlike this testing. Both use fast enough memory that it shouldn't effect the score much, but enough to get a 5% shift? Maybe.

Edit: This is the same reviewer that listed LP P-cores in their testing (which doesn't exist) and showed an IPC regression in the E-cores as well whereas Intel said they improved E-core IPC. Now, I don't necessarily take Intel at their word, but the other reviewer I mentioned did show an IPC increase in their testing of the E-cores, right in line with Intel's IPC claims. All of this leads me to believe this was simply faulty testing and there is no IPC regression in the P-cores and an IPC increase in the E-cores, which is basically what Intel said themselves.

Edit2: He also has entries like this in his table of SPECint scores:

View attachment 94872

How do you calculate IPC from a score if you don't know what the actual clock rate was when running the benchmark? Did he actually track the average clock speed or just use the mid point of his range (which would most likely be inaccurate for IPC calculation)? Too many questions and things that don't add up for me to trust his testing.

TBH, Intel started working on RWC even before RPL work started. So, in essence, RWC is actually GLC (plus some RPC improvements). MTL's IPC should be similar to RPC at a given clock. And it's not logical to expect it to match the higher-clocked RPC when MTL has clock regression. This I think was already discussed a few months back I think.

The more disappointing news is, even though there is a slight performance regression, I assumed that the new MTL architecture will offset that disadvantage with a large increase in efficiency. I mean a pretty massive gain considering all the power-saving/efficiency tech put into MTL. But it didn't pan out well.

As of now, MTL's efficiency looks like it's similar to or maybe slightly better than RPL. And thats not a good thing if you ask me.

Edit: Oops! wrong thread. Apologies. Best to continue this in Intel thread.

 

[FlameTail]

All these "nm" don't make sense anymore. It's been more than 20 years since node names actually represented transistor metrics. In Intel 20A, TSMC N2 & Samsung 2nm, the actual transistor is actually around 10X bigger (or more) I think. All these 20A, N2, SF2 are pure marketing tricks. I don't think we should take them seriously anymore going forward.

I think we all know that already.

What we want is for the foundries to align their naming schemes.

 

[moinmoin]

What we want is for the foundries to align their naming schemes.

It seems Samsung doesn't want to admit its own inferiority though. So they keep crying for attention.

The bad thing about it is that if Samsung at some point actually has something competitive with leading edge too many potential customers may not care anymore.

 

[SiliconFly]

I think we all know that already.

What we want is for the foundries to align their naming schemes.

Don't think they'll do that. Isn't good for their business.

 

[FlameTail]

It seems Samsung doesn't want to admit its own inferiority though. So they keep crying for attention.

The bad thing about it is that if Samsung at some point actually has something competitive with leading edge too many potential customers may not care anymore.

They will have lost reputation not only among semiconductor companies, but even the general tech community.

For instance, if you check out the Android tech communities in X or Reddit, you can see that the majority of people have less respect for Samsung Foundry, as they are aware of Samsung nodes' inferiority.

 

[Hitman928]

[Rumor] Meta may be switching from TSMC to Samsung to manufacture their custom chip designs:

Meta to partner with Samsung to reduce reliance on TSMC: presidential office

Meta founder and CEO Mark Zuckerberg indicated the U.S. multinational technology conglomerate's intention to work with Samsung Electronics in the artificial intelligence (AI) semiconductor sector to rely less on chip giant Taiwan Semiconductor Manufacturing Company, or TSMC, according to the...

www.koreatimes.co.kr

 

[igor_kavinski]

[Rumor] Meta may be switching from TSMC to Samsung to manufacture their custom chip designs

Where are these chip designers coming from? Isn't this supposed to be a black art of sorts or did someone opensource a recent chip design that everyone and their granny is coming out with their variation?