Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

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Vattila

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Oct 22, 2004
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Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).



What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!
 
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SteinFG

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Dec 29, 2021
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That so far raises more questions than it gives answers. If the form factor is indeed the same as previous TR gens, is it then based on Siena/SP6 with 6 channels? But how do they manage 96 cores/12 CCDs then, wouldn't that actually require Zen 4c CCDs, and then 6 of them? And how would it then differentiate between Pro and non-Pro if the max of 6 channels is already less than the previous TR Pro gen?

Could well mean that now both TR and TR Pro are truly platforms of their own, distinct from the existing server platforms. That's unexpected.
4844 pins of SP6/TR5 is enough for 128 lanes and 8 memory channels. AMD just downgraded SP6 to make it a relatively cheap platform
 

moinmoin

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Jun 1, 2017
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4844 pins of SP6/TR5 is enough for 128 lanes and 8 memory channels. AMD just downgraded SP6 to make it a relatively cheap platform
That's interesting though, making Siena/SP6 the cut down platform and WRX90 the full one, with TRX50 the even further cut down variant. I considered a continuation of SP3 instead, but you are right in pointing out the amount of pins which with SP6's 4844 is a significant increase over SP3's 4094 pins. And TR using Zen 4 whereas Siena uses Zen 4c means workstation/server are not exchangeable before binning like may have been done in previous TR gens.
 

StefanR5R

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Dec 10, 2016
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I gather that the I/O die, which AMD said is the same in EPYC 9004 and 8004, consists of 4 quadrants (like EPYC 7002's and 7003's) with one triple-channel memory controller in each quadrant (EPYC 7002 and 7003: one dual-channel MC in each quadrant; enhanced in 7003 to remove 7002's performance problems with memory populations other than 4 or 8 channels). It seems as if EPYC 8004 Siena has got two of the IOD quadrants enabled, at least as far as memory controllers are concerned.

From the rumors so far, Threadripper 7000 may have all 4 quadrants of the IO die enabled, but with fewer than 3 channels per MC routed out of the package.

Furthermore, there seem to be 3 GMI ports per IOD quadrant; EPYC 9004 SKUs use either 8 or all 12 of the GMI ports, 8004 apparently uses only up to 4 of them. It's not clear to me if these 4 GMI ports are associated with 4 or 2 quadrants of the IOD.

And finally, 9004's IOD has got 4 "P-links" and 4 "G-links". Each of these can be one PCIe root, with 16 lanes per root = 128 lanes in total. AFAIK either 48 or 64 of these lanes from "G-links" can be dedicated to xGMI lanes in dual-socket systems. EPYC 8004 Siena offers 96 PCIe lanes, therefore it needs to have 6 of the 4+4 P-/G-links enabled. So it looks as if 2 of the 4 IOD quadrants aren't completely disabled in Siena but still functional WRT some of the P-/G-links.

There were rumors about Threadripper 7000's PCIe lane counts, but who knows if these rumors weren't just outsiders' guesses in a bid for attention. Edit: And until now, Treadripper boards always came with a south bridge for extra I/O. I wonder if AMD keeps that or gets rid of it for the 7000 series.
 
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SteinFG

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Dec 29, 2021
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I gather that the I/O die, which AMD said is the same in EPYC 9004 and 8004, consists of 4 quadrants (like EPYC 7002's and 7003's) with one triple-channel memory controller in each quadrant (EPYC 7002 and 7003: one dual-channel MC in each quadrant; enhanced in 7003 to remove 7002's performance problems with memory populations other than 4 or 8 channels). It seems as if EPYC 8004 Siena has got two of the IOD quadrants enabled, at least as far as memory controllers are concerned.

From the rumors so far, Threadripper 7000 may have all 4 quadrants of the IO die enabled, but with fewer than 3 channels per MC routed out of the package.

Furthermore, there seem to be 3 GMI ports per IOD quadrant; EPYC 9004 SKUs use either 8 or all 12 of the GMI ports, 8004 apparently uses only up to 4 of them. It's not clear to me if these 4 GMI ports are associated with 4 or 2 quadrants of the IOD.

And finally, 9004's IOD has got 4 "P-links" and 4 "G-links". Each of these can be one PCIe root, with 16 lanes per root = 128 lanes in total. AFAIK either 48 or 64 of these lanes from "G-links" can be dedicated to xGMI lanes in dual-socket systems. EPYC 8004 Siena offers 96 PCIe lanes, therefore it needs to have 6 of the 4+4 P-/G-links enabled. So it looks as if 2 of the 4 IOD quadrants aren't completely disabled in Siena but still functional WRT some of the P-/G-links.

There were rumors about Threadripper 7000's PCIe lane counts, but who knows if these rumors weren't just outsiders' guesses in a bid for attention.
In 8004 all 4 quarters are working.
Each quarter has 2 working gmi links (for 8 total, 2 per Zen4c CCD)

Edit: I'm only talking about 64-core variant, 32-core has 2 CCDs, so there might be something different
 
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Timmah!

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Jul 24, 2010
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No prices announced. Which is... interesting.

Edit: AT updated their article. The 7960X (24 cores) is $1499. Available Nov 21st.
Thats actually fairly enticing. Or at least it would have been a year ago. I would have definitely considered it.

Now i have to wonder, if Zen5 16 core will be performance wise in multithread on par with 7960x. Like almost same score in Cinebench and whatnot.
 

StefanR5R

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Dec 10, 2016
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until now, Treadripper boards always came with a south bridge for extra I/O. I wonder if AMD keeps that or gets rid of it for the 7000 series.
They are keeping it but slimmed it down. The specs of the WRX90 southbridge...
https://images.anandtech.com/galleries/9379/Ryzen TR 7000 Pro Slide Deck 2 (14).jpg
...look oddly familiar. B650:
https://images.anandtech.com/doci/17585/SoC_26.png

I haven't seen any reports on a TRX50 southbridge yet, beyond that 4 PCIe lanes are on special duty on both the Pro and non-Pro Threadrippers.
https://images.anandtech.com/galleries/9379/Ryzen TR 7000 Pro Slide Deck 1 (31).jpg
 

Abwx

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StefanR5R

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Noctua released a new mounting kit to make their existing SP3/TR4 coolers, as well as LGA 4677/ LGA 4189/ LGA 3647 coolers, compatible with SP6/TR5:
https://noctua.at/en/nm-tr5-sp6-mounting-kit
According to them, this new mounting mechanism is needed for a higher required mounting pressure on SP6/TR5. Makes sense, given the increased pin count.

Also released:
  • NH-U14S TR5-SP6 --- this is just a NH-U14S DX-4677 but with SP6/TR5 mounting rails. Comes with two fans, unlike NH-U14S TR4-SP3 which is shipped with just one fan.
  • NH-D9 TR5-SP6 4U --- a NH-D9 DX-4677 4U but with SP6/TR5 mounting rails.

News item:
https://noctua.at/en/noctua-announces-cpu-coolers-for-amd-s-new-threadripper-and-epyc-processors
 

nicalandia

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Kepler_L2

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Sep 6, 2020
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well, zen4 16C more or less matched 24C TR 5965wx in cinebench MT, and since Zen5 was touted to be even bigger performance jump....
Zen4 had massive MT improvement due to combination of IPC gain, SMT yield increase and 5nm + higher power limit allowing up to 30% higher all-core boost clocks. Zen5 "just" has a big IPC increase and will primarily shine in ST or lightly threaded applications.
 

Timmah!

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Jul 24, 2010
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Zen4 had massive MT improvement due to combination of IPC gain, SMT yield increase and 5nm + higher power limit allowing up to 30% higher all-core boost clocks. Zen5 "just" has a big IPC increase and will primarily shine in ST or lightly threaded applications.
I am aware of that, and i agree, but i have seen people waxing lyrically about Zen5, maybe even before Zen4 was released, or shortly after, how Zen5 will be that "supercycle", thats gonna improve things drastically, after all the chief architect was excited about it...
and now it seems to turn out that it might bring less performance uplift that Zen4 brought, so maybe not so special after all? Or is it strictly because people are specifically enthusiastic about possible ST performance gains? Which, ultimately, may not be as big as they initially hyped to be.
 
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