View attachment 94376
Wait, is Family A0 --> Zen 6 or some typo?
Update:
This looks like a custom core/family probably
The only case for this in relationship to Zen5 is:
Family 0Ah 00h-0Fh => Sonoma Valley (Samsung 4nm SF4 Compact 1-fin Lib ::
https://ieeexplore.ieee.org/document/9830184 )
Family A0 -> Decimal 160, do to it being a 0.01, I think the A0h is potentially wrong. It is likely to be instead 0Ah -> Decimal 10. It might be that they copied over Bergamo's A0h. As leaping from 00h~1Fh space beyond 20h-9Fh space to A0h is a massive shift. Family 17h Model 160/A0h is Mendocino. However, it's PMC doesn't have tokens for schedulers instead being reserved only. So, it is definitely a quick Bergamo paste where it's A0h potentially replaced 0Ah.
1Ah = Zen5 High Performance cores
0Ah = Zen5 Low Power cores
Zen4's PMC EX Dispatch has tokens for four schedulers. Which Zen4 has:
While this design has tokens for two schedulers one for ALU tokens and one for AGU tokens. Which will make it like Bobcat and Jaguar:
Most of it is basically 1:1 with Zen4 otherwise.
Integer Scheduler is likely to be paired with 6 ALUs
Address Scheduler is likely to be paired with 4 AGUs
It is generally more power-efficient to have a unified scheduler for low-power.
Should functionally be Zen5 except for low-macro count and be extremely synthesized(extra fast ttm vs hybrid hand-tuned/synthesized HP cores)
Family 15h => First Dense core in same family // Zen4/Zen4c and Zen5/Zen5c keeping same family is caused by this.
Family 10h/11h => First HP/LP cores // Zen5 HighPerf/Dense are same family, but 10h/11h, 15h/14h, and 17h/16h denote that Low-power cores do not share family. Thus, Zen5/5c would be Family 1Ah and the Zen5 low power option would be Family 0Ah.
Further is Zen5/5c is "high complexity" which can only be fabbed at TSMC while Zen5 low power would be "low complexity" thus can be fabbed at Samsung.