Given that Neoverse V2 reduced SVE width I wouldn't hold my breath.consumer ARM CPUs (Cortex, Apple Silicon, Oryon) ever get 256 bit vector SIMD? If so, when?
Not in a single cycle, but in total ops yes.consumer ARM CPUs (Cortex, Apple Silicon, Oryon) ever get 256 bit vector SIMD? If so, when?
I want to see a 16 wide core this decade.
Come on, we all know the Mill will make all of this obsolete(Multiflow Trace went to 28-wide in the 80s...)
Simply not feasible without destroying clock frequency scaling.I want to see a 16 wide core this decade.
Even worse would be power consumption. And the fact you'd have to predict 3 or 4 branches per cycle on average...Simply not feasible without destroying clock frequency scaling.
Simply not feasible without destroying clock frequency scaling.
They could use a thermoelectric thingamajig to use the heat from one core to power another coreEven worse would be power consumption.
Didn't AMD say that Ryzen uses an adaptive AI-based branch predictor? Is that the same thing as the perceptron? Something that Intel has yet to implement?
TAGE and its derivatives remain the best, it looks like black magic. I think it's now used by all major CPU designs. And it's not patent encumbered. Kudos to SeznecThey did use perceptron with Cats and Bulldozer and Zen1 if remember correctly but Zen2/3 switched to more advanced tage predictor.
Wow. That guy is a giant and a legend in his field. Basically decided to fight Amdahl's law. Really weird that I never heard of him before. His textbooks (if any) must be recommended reading in silicon design circles.Kudos to Seznec
Even worse would be power consumption. And the fact you'd have to predict 3 or 4 branches per cycle on average...
I am guessing 4×128 just like the others.No idea what Oryon/Phoenix µArch specifics are at this point, probably we will find out at this years Hotchips
ARM got a lot out of 4 wide µArch, as have AMD.If going wider is out of the table, then what are ARM CPU makers gonna do with their flagship cores to get significant increases in IPC?
If going wider is out of the table, then what are ARM CPU makers gonna do with their flagship cores to get significant increases in IPC?
ARM Cortex X4 : 10 wide
Apple A17 P : 9 wide
Qualcomm Oryon : 8 wide (guess)
These ARM CPUs are already much wider than x86 rivals.
Just 130?Clearly, going 130-wide is all that's needed
IMHO unlikely.Cardyak’s Microarchitecture Cheat Sheet
docs.google.com
Repository containing architecture details of cores.
Cortex X4 is 10 wide executor and 10 wide dispatcher.
The widest core in this list.
Crazy.
Will Blackhawk (Cortex X5) go even wider?
Sadly thermoelectric efficiency is truly terrible for either cooling or power generation - a problem that NASA has been seeking a definitive solution to since likely before any of us were born.They could use a thermoelectric thingamajig to use the heat from one core to power another core
If I remember correctly they increased decode width to 3 with A75.IMHO unlikely.
When we saw A72 -> A73 it was Austin -> Sophia and we saw a 'regression' in core width from 3 wide to 2 wide, but a more efficient core overall, and Sophia got even more still out of 2 wide with A75.
I had thought so myself previously but when I brought it up someone told me that it was still 2 wide to my surpriseIf I remember correctly they increased decode width to 3 with A75.