Discussion Future ARM Cortex + Neoverse µArchs Discussion

[FlameTail]

consumer ARM CPUs (Cortex, Apple Silicon, Oryon) ever get 256 bit vector SIMD? If so, when?

 

[Nothingness]

consumer ARM CPUs (Cortex, Apple Silicon, Oryon) ever get 256 bit vector SIMD? If so, when?

Given that Neoverse V2 reduced SVE width I wouldn't hold my breath.

 

[soresu]

consumer ARM CPUs (Cortex, Apple Silicon, Oryon) ever get 256 bit vector SIMD? If so, when?

Not in a single cycle, but in total ops yes.

X1 has 4x 128 bit NEON units as did Apple's equivalent at the time.

Vector SIMD is also pretty much redundant language I believe.

SIMD is basically identical math operations on multiple numbers/data in 1 instruction.

No idea what Oryon/Phoenix µArch specifics are at this point, probably we will find out at this years HotChips.

 

[SarahKerrigan]

I want to see a 16 wide core this decade.

We don't always get everything we want.

(Multiflow Trace went to 28-wide in the 80s...)

 

[Nothingness]

(Multiflow Trace went to 28-wide in the 80s...)

Come on, we all know the Mill will make all of this obsolete

 

[soresu]

I want to see a 16 wide core this decade.

Simply not feasible without destroying clock frequency scaling.

 

[Nothingness]

Simply not feasible without destroying clock frequency scaling.

Even worse would be power consumption. And the fact you'd have to predict 3 or 4 branches per cycle on average...

 

[naukkis]

Simply not feasible without destroying clock frequency scaling.

We only need ISA to split register file for such a many in-clock instruction support for making it feasible. Only Risc-V do support such a schemes - at least somehow.

 

[igor_kavinski]

Even worse would be power consumption.

They could use a thermoelectric thingamajig to use the heat from one core to power another core

Silicon integrated circuit thermoelectric generators with a high specific power generation capacity - Nature Electronics

Thermoelectric generators based on nanostructured silicon thermopiles, which are fabricated on an industrial silicon CMOS process line and are thus compatible with integrated circuit technology, exhibit a high specific power generation capacity of up to 29 μW cm−2 K−2 near room temperature.

www.nature.com

 

[igor_kavinski]

https://www.cs.utexas.edu/~lin/papers/hpca01.pdf

Didn't AMD say that Ryzen uses an adaptive AI-based branch predictor? Is that the same thing as the perceptron? Something that Intel has yet to implement?

 

[naukkis]

https://www.cs.utexas.edu/~lin/papers/hpca01.pdf

Didn't AMD say that Ryzen uses an adaptive AI-based branch predictor? Is that the same thing as the perceptron? Something that Intel has yet to implement?

They did use perceptron with Cats and Bulldozer and Zen1 if remember correctly but Zen2/3 switched to more advanced tage predictor.

 

[Nothingness]

They did use perceptron with Cats and Bulldozer and Zen1 if remember correctly but Zen2/3 switched to more advanced tage predictor.

TAGE and its derivatives remain the best, it looks like black magic. I think it's now used by all major CPU designs. And it's not patent encumbered. Kudos to Seznec

 

[igor_kavinski]

Kudos to Seznec

Wow. That guy is a giant and a legend in his field. Basically decided to fight Amdahl's law. Really weird that I never heard of him before. His textbooks (if any) must be recommended reading in silicon design circles.

 

[SarahKerrigan]

Even worse would be power consumption. And the fact you'd have to predict 3 or 4 branches per cycle on average...

Just elide short branches to predicates to increase median BB length to 8-12 or higher, and software-pipeline the crap out of loops as a source of cheap low-branch ILP. Foolproof. Worked great last time.

Well, except when it didn't.

 

[FlameTail]

No idea what Oryon/Phoenix µArch specifics are at this point, probably we will find out at this years Hotchips

I am guessing 4×128 just like the others.

 

[FlameTail]

If going wider is out of the table, then what are ARM CPU makers gonna do with their flagship cores to get significant increases in IPC?

ARM Cortex X4 : 10 wide
Apple A17 P : 9 wide
Qualcomm Oryon : 8 wide (guess)

These ARM CPUs are already much wider than x86 rivals.

 

[soresu]

If going wider is out of the table, then what are ARM CPU makers gonna do with their flagship cores to get significant increases in IPC?

ARM got a lot out of 4 wide µArch, as have AMD.

It's far too early to talk about what they all need to do in the future given a much wider foundation to build from.

Likewise Apple were pretty stable at 6 wide for years and got good gains for a while.

 

[SarahKerrigan]

If going wider is out of the table, then what are ARM CPU makers gonna do with their flagship cores to get significant increases in IPC?

ARM Cortex X4 : 10 wide
Apple A17 P : 9 wide
Qualcomm Oryon : 8 wide (guess)

These ARM CPUs are already much wider than x86 rivals.

Prefetch
Branch prediction
Cache capacity and performance
Functional unit mix and latencies
Structure sizes
Improved fusion
Multithreading?

You know, nothing much. Clearly, going 130-wide is all that's needed.

 

[soresu]

Clearly, going 130-wide is all that's needed

Just 130?

I had something a little more radical in mind....

 

[naukkis]

Main bottleneck for going wider is register file. If whole register file is general purpose for all instructions going wider needs more ports to that big fat uniform register file. Solution is simple, split register file so every instruction doesn't have access to whole register file. Doing so mean for hardware that alus and register files became independent from each other and increasing such a separate complexes to execution core won't increase it's complexity pretty much at all. Basically for software execution that means that thread has sub-threads that can have fast access to their parts of registers and bit slower interaction for other parts of register file. Risc-V has given a though to that register file splitting scheme - so far all risc-v hardware is still made for unified register file model but risc-V at least gives a pathway to do split register file designs too.

 

[FlameTail]

3 more months to go until Cortex X5 launch.

There was a leaked GB6 score of D9400 with X5 scoring only 2700 in ST. That's disappointing and not the kind of performance doesn't sound like one befitting the title of "custom-core killer".

Even if the performance is not gonna catch upto Apple (assuming the leak holds to be true), I'd still call it a W if ARM can match or exceed Apple's efficiency.

Because, while X4 brought a substantial performance improvement, they sold their efficiency to the devil to do so.

 

[soresu]

Microarchitecture Cheat Sheet - Google Drive

docs.google.com

Repository containing architecture details of cores.

Cortex X4 is 10 wide executor and 10 wide dispatcher.

The widest core in this list.

Crazy.

Will Blackhawk (Cortex X5) go even wider?

IMHO unlikely.

When we saw A72 -> A73 it was Austin -> Sophia and we saw a 'regression' in core width from 3 wide to 2 wide, but a more efficient core overall, and Sophia got even more still out of 2 wide with A75.

If X5/Blackhawk is truly Sophia's ground up core then I would not be surprised to see a similar change back to 7-9 wide design, or at worst no change from 10 wide.

I would hope also that the A730/Chaberton core is a significant leap in perf/watt over A720 given how meager the improvements have been to their big A cores of late - as it would be a shame to catch Apple on the high end only to lose miserably to them on the low end.

 

[soresu]

They could use a thermoelectric thingamajig to use the heat from one core to power another core

Sadly thermoelectric efficiency is truly terrible for either cooling or power generation - a problem that NASA has been seeking a definitive solution to since likely before any of us were born.

If it were even just as efficient as a modern steam turbine generator system then radioisotope thermoelectric generators (RTGs) for Mars rovers could be at least 3 times lower volume/mass for the same output wattage.

 

[naukkis]

IMHO unlikely.

When we saw A72 -> A73 it was Austin -> Sophia and we saw a 'regression' in core width from 3 wide to 2 wide, but a more efficient core overall, and Sophia got even more still out of 2 wide with A75.

If I remember correctly they increased decode width to 3 with A75.

 

[soresu]

If I remember correctly they increased decode width to 3 with A75.

I had thought so myself previously but when I brought it up someone told me that it was still 2 wide to my surprise