20% sounds about right, even if they made it all up. 10% would be considered failure by most people.So RGT is the source. . .
The last few pages of this thread have been:So RGT is the source. . .
And then there are those of use that say "wait until the retail benchmarks come in. Also, the 40% could have been MT ????? beta bios ??? and a thousand other things.The last few pages of this thread have been:
Person A: So RTG says that Zen 5 has 40% IPC gains.
Person B: No way, I saw another article that said it only has 20% IPC gains. Here's the article:
The article: "RedGamingTech has dropped bombshells..."
Yeah but noone wants to sit next to those kinda folk on the hype train when the party is at the front where we can see the usual suspects adding fuel to the fireAnd then there are those of use that say "wait until the retail benchmarks come in. Also, the 40% could have been MT ????? beta bios ??? and a thousand other things.
Person C: hey, that quote that RGT is using... is from Anandtech forums!The last few pages of this thread have been:
Person A: So RTG says that Zen 5 has 40% IPC gains.
Person B: No way, I saw another article that said it only has 20% IPC gains. Here's the article:
The article: "RedGamingTech has dropped bombshells..."
We've come full circle where we can't even recognise our exaggerated rumoursPerson C: hey, that quote that RGT is using... is from Anandtech forums!
There you go. We are the prophecy. We are the chosen. There is no spoon.
Person D: Hey AMD used my forum post to name their next CPU core! 😂Person C: hey, that quote that RGT is using... is from Anandtech forums!
They did. It is called “the stock market”.Vegas bookies need to get in on this.
One may even call it the rumor mill Ouroboros.We've come full circle where we can't even recognise our exaggerated rumours
Dear sir, AMD cpu benchmark leaks are never late; nor are they early, they arrive precisely when they mean toYeah but noone wants to sit next to those kinda folk on the hype train when the party is at the front where we can see the usual suspects adding fuel to the fire
I swear AMD has invented a time slowing down machine. The closer we get to the big reveal day, the slower the days flow. Lisa Su has much to answer for.
The Computex Keynote is always filled with surprises and is considered to be the best time to announce new products. In 2022, AMD announced Ryzen 6000 PRO series, the low-power APU called Mendocino. The company also announced Smart Access Store technology and several AMD Advantage laptops.
Don't forget the 10%-15% st uplift with clock regression priced at $999So the Zen5 DT store availability in April 2024 is only about 1-2 months away.
Just wonder if anyone has found any pre-order links on e.g. Amazon or Micro Center yet?
that would be a bulldozer level self own by amd 😂Don't forget the 10%-15% st uplift with clock regression priced at $999
Well that's definitely coming according to some peoplethat would be a bulldozer level self own by amd 😂
Not entirely true. There is a reason many Linux distros are now being shipped in x86-64-v1, x86-64-v2, x86-64-v3.Because you don't want to put things in your ISA that require recompilation to benefit from them.
You know that ISA don't have to change a bit but as execution hardware changes there's a need for recompilation to extract hardware full performance?
I was talking about something a bit different, though admittedly that wasn't clear in the message you quoted (but there was a context in the discussion). The thing is that if an ISA requires a lot of work from the compiler to get good performance and if extensions are published that require recompilation then you have an issue.Not entirely true. There is a reason many Linux distros are now being shipped in x86-64-v1, x86-64-v2, x86-64-v3.
I was talking about micro-architectural features visible at the ISA level that require compilation.
What make you think such a scheme isn't already used without being visible at the ISA level? Did you search for patents (since I work in a CPU company, I'm not allowed to look at patents, so I can't point you to existing ones and even can't say if any exists)?Registers clustering is actually very special case. Code will be 100% compatible for all hardware and software whether it is compiled clustered or not. Even performance in non-clustered devices should not decrease, it just gives hardware a possibility to go wider designs. And with with register-renaming hardware cpu can also switch from clustered to non-clustered execution dynamically as it needs. But for executing clustering register use will let hardware to split it's executions resources for more performance/higher clocks/better efficiency by disabling/enabling execution clusters. I actually have to wonder why such a scheme isn't already used - did Intel Epic frighten developers to even trying to use such a trivial possibilities to make execution engine simpler?
What make you think such a scheme isn't already used without being visible at the ISA level? Did you search for patents (since I work in a CPU company, I'm not allowed to look at patents, so I can't point you to existing ones and even can't say if any exists)?
Companies tend to tell as little as possible about their micro arch to avoid being attacked by predatory troll patent houses. That explains people trying to reverse engineer CPU performance find oddities they can't explain with existing informationYeah, I too suspected that such a simple solution should have been used for ages now. But cpu optimizing guides tell about everything how cpu's execute their instructions and handle registers - and at least I haven't found any notes for any kind of register clustering. General purpose registers are of course preferred for programmer but making registers little less general would open quite a lot of hardware optimization possibilities.
Companies tend to tell as little as possible about their micro arch to avoid being attacked by predatory troll patent houses. That explains people trying to reverse engineer CPU performance find oddities they can't explain with existing information